0241cbb9d6
Add resources and information for the UART deviecs on the S3C64XX CPUs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Common IRQ support
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*/
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#ifndef __ASM_PLAT_S3C64XX_IRQS_H
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#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S3C_IRQ_OFFSET (32)
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#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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* are not in the same order as the S3C24XX series! */
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#define IRQ_S3CUART_BASE0 (16)
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#define IRQ_S3CUART_BASE1 (20)
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#define IRQ_S3CUART_BASE2 (24)
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#define IRQ_S3CUART_BASE3 (28)
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#define UART_IRQ_RXD (0)
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#define UART_IRQ_ERR (1)
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#define UART_IRQ_TXD (2)
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#define UART_IRQ_MODEM (3)
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#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
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/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
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* we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
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* which we place after the pair of VICs. */
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#define S3C_IRQ_EINT_BASE S3C_IRQ(64)
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#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
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/* Define NR_IRQs here, machine specific can always re-define.
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* Currently the IRQ_EINT27 is the last one we can have. */
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#define NR_IRQS (S3C_EINT(27) + 1)
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#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
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