cee4cca740
* git://git.infradead.org/hdrcleanup-2.6: (63 commits) [S390] __FD_foo definitions. Switch to __s32 types in joystick.h instead of C99 types for consistency. Add <sys/types.h> to headers included for userspace in <linux/input.h> Move inclusion of <linux/compat.h> out of user scope in asm-x86_64/mtrr.h Remove struct fddi_statistics from user view in <linux/if_fddi.h> Move user-visible parts of drivers/s390/crypto/z90crypt.h to include/asm-s390 Revert include/media changes: Mauro says those ioctls are only used in-kernel(!) Include <linux/types.h> and use __uXX types in <linux/cramfs_fs.h> Use __uXX types in <linux/i2o_dev.h>, include <linux/ioctl.h> too Remove private struct dx_hash_info from public view in <linux/ext3_fs.h> Include <linux/types.h> and use __uXX types in <linux/affs_hardblocks.h> Use __uXX types in <linux/divert.h> for struct divert_blk et al. Use __u32 for elf_addr_t in <asm-powerpc/elf.h>, not u32. It's user-visible. Remove PPP_FCS from user view in <linux/ppp_defs.h>, remove __P mess entirely Use __uXX types in user-visible structures in <linux/nbd.h> Don't use 'u32' in user-visible struct ip_conntrack_old_tuple. Use __uXX types for S390 DASD volume label definitions which are user-visible S390 BIODASDREADCMB ioctl should use __u64 not u64 type. Remove unneeded inclusion of <linux/time.h> from <linux/ufs_fs.h> Fix private integer types used in V4L2 ioctls. ... Manually resolve conflict in include/linux/mtd/physmap.h
224 lines
9.1 KiB
C
224 lines
9.1 KiB
C
/* include/asm-arm/arch-lh7a40x/registers.h
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*
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* Copyright (C) 2004 Coastal Environmental Systems
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* Copyright (C) 2004 Logic Product Development
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <asm/arch/constants.h>
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#ifndef __ASM_ARCH_REGISTERS_H
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#define __ASM_ARCH_REGISTERS_H
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/* Physical register base addresses */
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#define AC97C_PHYS (0x80000000) /* AC97 Controller */
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#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
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#define USB_PHYS (0x80000200) /* USB Client */
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#define SCI_PHYS (0x80000300) /* Secure Card Interface */
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#define CSC_PHYS (0x80000400) /* Clock/State Controller */
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#define INTC_PHYS (0x80000500) /* Interrupt Controller */
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#define UART1_PHYS (0x80000600) /* UART1 Controller */
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#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
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#define UART2_PHYS (0x80000700) /* UART2 Controller */
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#define UART3_PHYS (0x80000800) /* UART3 Controller */
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#define DCDC_PHYS (0x80000900) /* DC to DC Controller */
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#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
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#define SSP_PHYS (0x80000b00) /* Synchronous ... */
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#define TIMER_PHYS (0x80000c00) /* Timer Controller */
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#define RTC_PHYS (0x80000d00) /* Real-time Clock */
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#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
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#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
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#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
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#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
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#define WDT_PHYS (0x80001400) /* Watchdog Timer */
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#define SMC_PHYS (0x80002000) /* Static Memory Controller */
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#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
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#define DMAC_PHYS (0x80002800) /* DMA Controller */
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#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
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/* Physical registers of the LH7A404 */
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#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
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#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
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#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
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#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
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/*#define KBD_PHYS (0x80000e00) */
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/*#define LCDICP_PHYS (0x80001000) */
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/* Clock/State Controller register */
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#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
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#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
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#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
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#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
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#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
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#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
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#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
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#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
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#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
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#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
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#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
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#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
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#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
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#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
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#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
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#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
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#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
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#define CSC_PWRSR_CHIPMAN_SHIFT (24)
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#define CSC_PWRSR_CHIPMAN_MASK (0xff)
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#define CSC_PWRSR_CHIPID_SHIFT (16)
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#define CSC_PWRSR_CHIPID_MASK (0xff)
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#define CSC_USBDRESET_APBRESETREG (1<<1)
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#define CSC_USBDRESET_IORESETREG (1<<0)
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/* Interrupt Controller registers */
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#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
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#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
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#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
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#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
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/* Vectored Interrupted Controller registers */
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#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
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#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
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#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
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#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
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#define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
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#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
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#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
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#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
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#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
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#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
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#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
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#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
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#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
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#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
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#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
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#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
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#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
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#define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
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#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
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#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
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#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
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#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
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#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
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#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
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#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
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#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
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#define VIC_CNTL_ENABLE (0x20)
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/* USB Host registers (Open HCI compatible) */
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#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
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/* GPIO registers */
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#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
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#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
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#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
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#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
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#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
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#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
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#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
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#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
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#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
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#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
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#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
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#define GPIO_PED __REG(GPIO_PHYS + 0x20)
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/* Static Memory Controller registers */
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#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
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#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
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#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
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#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
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#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
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#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
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#ifdef CONFIG_MACH_KEV7A400
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# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
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# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
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# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
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# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
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# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
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# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
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# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
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# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
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# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
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# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
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# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
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# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
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#endif
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#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
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# define CPLD_CONTROL __REG16(CPLD02_PHYS)
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# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
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# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
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# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
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# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
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# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
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# define CPLD_FLASH __REG16(CPLD10_PHYS)
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# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
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# define CPLD_REVISION __REG16(CPLD14_PHYS)
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# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
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# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
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# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
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#endif
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/* Timer registers */
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#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
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#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
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#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
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#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
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#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
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#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
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#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
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#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
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#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
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#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
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#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
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#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
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#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
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#define TIMER_C_ENABLE (1<<7)
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#define TIMER_C_PERIODIC (1<<6)
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#define TIMER_C_FREERUNNING (0)
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#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
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#define TIMER_C_508KHZ (0x08)
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/* GPIO registers */
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#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
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#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
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#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
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#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
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#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
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#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
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#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
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#endif /* _ASM_ARCH_REGISTERS_H */
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