Jens Renner \(EFE\) 3a5395b3d5 net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR ... This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not setting them correctly on others (like TI DP83630) makes the PHY fall back to 10M HDX mode which should be avoided. Tested for TI DP83630 PHY on Microblaze platform. Signed-off-by: Jens Renner <renner@efe-gmbh.de> Tested-by: Michal Simek <monstr@monstr.eu> Signed-off-by: David S. Miller <davem@davemloft.net>		2013-06-04 17:21:28 -07:00
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Kconfig	net: ethernet: xilinx: Do not use axienet on PPC	2013-01-10 14:28:26 -08:00
Makefile	drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver	2012-01-25 16:59:47 -05:00
ll_temac.h	…
ll_temac_main.c	net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*	2013-04-19 14:45:26 -04:00
ll_temac_mdio.c	…
xilinx_axienet.h	drivers/net/ethernet/xilinx/axi ethernet: Correct Copyright	2012-04-13 13:58:42 -04:00
xilinx_axienet_main.c	drivers:net: dma_alloc_coherent: use __GFP_ZERO instead of memset(, 0)	2013-03-17 12:50:24 -04:00
xilinx_axienet_mdio.c	drivers/net/ethernet/xilinx/axi ethernet: Correct Copyright	2012-04-13 13:58:42 -04:00
xilinx_emaclite.c	net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR	2013-06-04 17:21:28 -07:00