This adds support for the SH7263 (SH-2A) CPU.
This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.
No visibly nasty surprises, yet..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH-2A supports both 16 and 32-bit instructions, add a simple helper
for figuring out the instruction size in the places where there are
hardcoded 16-bit assumptions.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements initial support for the SH7206 (SH-2A) and SH7619
(SH-2) MMU-less CPUs.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt