Interpretation of 'row' and 'col' got reversed in matrix keymap
framework. Also last element '0', present in keymap array, is no
more needed.
Correcting zoom2 keyboard keymap accordingly.
Signed-off-by: Vimal Singh <vimalsingh@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fixes a bug where scheduling is delayed until next wakeup due to race
condition (e.g. interrupt requests scheduling just before omap_sram_idle
is entered.)
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch removes the check to see if some functional clocks are
still enabled before entering sleep. This is no longer needed when
using safe state (C1) that keeps CORE active.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
It is more efficient to use pwrdm_set_next_pwrst for mpu, core and neon
instead of set_pwrdm_state in idle loop. It is anyway known that those are
active in idle loop. So no need to use set_pwrdm_state.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The current definition of C-states starts from base 1.
Whereas, the cpuidle driver uses base 0. This patch
eliminates need for explicit mapping (add/ sbutract)
due to different base values.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch introduces a new C state which allows MPU to go to WFI but keeps
the core domain active. This offers a much better wakeup latency (3us vs
10s of us for the current C1) at the cost of a higher power consumption.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Previously omap3_idle_init() was called in device_init, while
omap_pm_init() is called at late_initcall. This causes the cpu idle
driver to call omap_sram_idle before it is properly initialized. This
patch fixes the issue by moving omap3_idle_init into omap3_pm_init.
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Use the activity check for states C2 and C3 as well. This is
primarily to prevent deeper states during UART activity.
Also, if a different state is chosen than the target state, update the
'last_state' accordingly so that CPUidle state accounting is coorect.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch adds support and enables state C4(MPU RET + CORE RET)
and MPU OFF states (C3 and C5.)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Basic CPUidle driver for OMAP3 with deepest sleep state supported
being MPU CSWR.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Due to an OMAP3 errata (1.142), on HS/EMU devices SDRC should be
programed to issue automatic self refresh on timeout
of AUTO_CNT = 1 prior to any transition to OFF mode.
This is needed only on sil rev's ES3.0 and above.
This patch enables the above needed WA in the SDRC power register
value stored in scratchpad, so that ROM code restores this value
in SDRC POWER on the wakeup path.
The original SDRC POWER register value is stored and restored back
in omap_sram_idle() function.
This fixes some random crashes observed while stressing suspend
on HS/EMU devices.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
wake up enabling. It needs to be enabled when entering
retention or off state, otherwise waking up might not work
in all situations.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
MPU and CORE should stay awake if there is CAM domain ACTIVE. This is
because that module doesn't have wake-up capability.
This should replace the patch that is currently in the PM branch.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP3 can't generate wakeups in this state, thus it is not permitted.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Using debugfs, export a configurable wakeup timer to be used to
wakeup system from suspend.
If a non-zero value is written to
/debug/pm_debug/wakeup_timer_seconds, A timer wakeup event will wake
the system and resume after the configured number of seconds.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Allow enable/disable of low-power states during idle. To
enable low-power idle:
echo 1 > /debug/pm_debug/sleep_while_idle
to disable:
echo 0 > /debug/pm_debug/sleep_while_idle
Also allow enable/disable of OFF-mode. To enable:
echo 1 > /debug/pm_debug/enable_off_mode
to disable:
echo 0 > /debug/pm_debug/enable_off_mode
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Errata: ES3.0, ES3.1 SDRC not sending auto-refresh when OMAP wakes-up
from OFF mode
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The reboot mode can be communicated to a bootloader (or the
kernel itself) with a scratchpad register. This functionality
is especially useful, if userspace is allowed to change
the reboot mode.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The CM_CLKEN_PLL register saved in scratchpad memory
was wrongly using offset of 0x0004 instead of 0x0000.
The effect of this was that boot ROM code would
restore the wrong value when waking up from off mode.
This wrong value, however, will be overwritten by
prcm context restore. Still, a short period of wrong
clock settings in CM_CLKEN_PLL remained between ROM
code and prcm context restore. This is fixed by the
patch.
Problem reported by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The SMS_SYSCONFIG register gets reset in off mode, added a
save/restore mechanism for that.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.
A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.
There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Fix for ES3.0 bug: SDRC not sending auto-refresh when OMAP wakes-up
from OFF mode (warning for HS devices.)
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The function omap3_save_secure_ram() is now called only once during
the initialization of the device and consequent sleep cycles will
re-use the same saved contents for secure RAM. Users who need secure
services should do secure RAM saving before entering off-mode, if a
secure service has been accessed after last save.
There are both latency and reliability issues with saving secure RAM
context in the idle path. The context save uses a hardware resource
which takes an order of hundreds of milliseconds to initialize after a
wake up from off-mode, and also there is no way of checking whether it
is ready from kernel side or not. It just crashes if you use it too
quickly
Additional fix to ensure scratchpad save is done after secure
RAM by Roger Quadros.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
For HS/EMU devices, some additional resources need to be
saved/restored for off-mode support. Namely, saving the secure RAM
and a pointer to it in the scratchpad.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
For HS/EMU devices, these additional features are also used:
- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restore
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for CORE powerdomain resources in order
to support off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Adds a 'save_state' option when calling into SRAM idle function
and adds some minor cleanups of SRAM asm code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
During the MMU restoration on the restore path from MPU OFF, the page
table entry for the page consisting of the code being executed is
modified to make MMU return VA=PA.
The MMU is then enabled and the original entry is being stored in
scratchpad. This patch reads the original values stored in
scratchpad, and restores them back.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Expand the powerdomains handled in the idle path to include PER, NEON
and CORE. This includes properly clearing the previous powerstates,
linking NEON state to MPU state and calling the UART prepare functions
for only the appropraite powerdomain transitions (CORE for UART1,2,
PER for UART3.)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Generalize the copy of SRAM functions into omap_push_sram_idle()
so it can be used on init but also after off-mode transitions.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for the System Control Module to suport
off-mode.
ETK and debobs definitions added by Peter De Schrijver.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch populates the scratchpad contents as expected by the
bootROM code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for PRCM module to support off-mode.
Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero
Kristo.
Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add context save and restore for the INTC module to support off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch adds the context save and restore functions for GPMC to
enable off-mode.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The host port power is enabled by driving the nEN_USB_PWR low as stated in
the comment. This fix is originally from Steve Sakoman <steve@sakoman.com>.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Cc: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The original TWL4030 keypad driver from linux-omap used KEY()
macro defined as (col, row), but while it was merged upstream
it was changed to use matrix keypad infrastructure, which uses
(row, col) format. Update the keymap in board file to match
layout of mainline driver.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the resource_size function instead of manually calculating the
resource size. This reduces the chance of introducing off-by-one errors
and actually fixes one in mailbox.c.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Tony Lindgren <tony@atomide.com>
audio_mclk value is going to be handled by the
twl4030-codec MFD driver, configure the correct
value for boards, which is using the twl4030 audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add needed platform data for the twl4030_codec MFD on boards,
where the audio part of the twl4030 codec is used.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch removes the unnecessary UART4 platform which is under
data is wrong because of this
There is a separate platform structure for UART4
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-By: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch enables omap_serial_early_init() function for OMAP4430
SDP. Without this the bootup would throw oops in omap_serial_init().
Note that the ifndef CONFIG_ARCH_OMAP4 is split into two sections
to enable omap_serial_early_init(). This ifndef cannot be removed
until omap4 clock framework is implemented.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-By: Tony Lindgren <tony@atomide.com>
Reviewed-By: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
UART3 is in the PER powerdomain. If PER goes idle/inactive
independently of CORE, for UART3 to wakeup it must have its wakeup
enable bits setup in PM_WKEN_PER. This patch enables these bits.
The reason it works when PER and CORE work together is because when
CORE goes inactive/retention, the IOPAD wakeups are enabled and
trigger UART3 wakeup.
Without this patch, when the UART inactivity timer fires for UART3,
its clocks are disabled and it's unable to wakeup so will be unusable
until PER is awoken by another source.
Another way of testing is by keeping CORE on during suspend but
allowing PER to hit retention
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
then enter suspend
# echo mem > /sys/power/state
Without this patch, UART3 will be unable to wakeup the system.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Only mach-omap2 boards are currently using matrix_keypad. Allow
mach-omap1 boards to use the old style keypad.h without breaking.
Created against linux-2.6.32-rc5.
Compile tested with omap_3430sdp_defconfig and rx51_defconfig.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the remaining headers under plat-omap/include/mach
to plat-omap/include/plat. Also search and replace the
files using these headers to include using the right path.
This was done with:
#!/bin/bash
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
headers=$(cd $mach_dir_old && ls *.h)
omap_dirs="arch/arm/*omap*/ \
drivers/video/omap \
sound/soc/omap"
other_files="drivers/leds/leds-ams-delta.c \
drivers/mfd/menelaus.c \
drivers/mfd/twl4030-core.c \
drivers/mtd/nand/ams-delta.c"
for header in $headers; do
old="#include <mach\/$header"
new="#include <plat\/$header"
for dir in $omap_dirs; do
find $dir -type f -name \*.[chS] | \
xargs sed -i "s/$old/$new/"
done
find drivers/ -type f -name \*omap*.[chS] | \
xargs sed -i "s/$old/$new/"
for file in $other_files; do
sed -i "s/$old/$new/" $file
done
done
for header in $(ls $mach_dir_old/*.h); do
git mv $header $plat_dir_new/
done
Signed-off-by: Tony Lindgren <tony@atomide.com>
Create the headers needed for compiling under
mach-omap1/include/mach and mach-omap2/include/mach.
This was done with the following script:
#!/bin/bash
mach_files="clkdev.h gpio.h hardware.h io.h irqs.h memory.h \
smp.h system.h timex.h uncompress.h vmalloc.h"
omaps="mach-omap1 mach-omap2"
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
mkdir -p $plat_dir_new
git add $plat_dir_new
for dir in $omaps; do
mach_dir_new="arch/arm/$dir/include/mach"
for header in $mach_files; do
file="$mach_dir_new/$header"
if [ ! -f $file ]; then
echo -ne "/*\n * $file\n */\n\n#include <plat/$header>\n" > $file
git add $file
if [ ! -f $plat_dir_new/$header ]; then
git mv $mach_dir_old/$header $plat_dir_new/$header
fi
fi
done
done
Signed-off-by: Tony Lindgren <tony@atomide.com>
Earlier patch "omap: Remap L3, L4 to get more kernel io address space"
changed the VMALLOC_END.
However, this change causes problems on mach-omap1:
BUG: mapping for 0xe0000000 at 0xe0000000 overlaps vmalloc space
BUG: mapping for 0xe1000000 at 0xe1000000 overlaps vmalloc space
Fix this by creating separate vmalloc.h files for mach-omap1
and mach-omap2.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds few necessary peripherals for OMAP4.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the low level debug UART io address as per this series.
The change is essential to have CONFIG_DEBUG_LL working.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch splits OMAP2_IO_ADDRESS to OMAP2_L3_IO_ADDRESS and
OMAP2_L4_IO_ADDRESS to reclaim more IO space.
The omap_read*() and omap_write*() functions will work only over
L4 address space. Current omap kernel stack uses these functions
only to access registers over L4 io address space
Note that these macros should only be used when ioremap does
not work. Please use ioremap instead in all new code.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
clock24xx.c is missing a omap2_init_clk_clkdm() in its
omap2_clk_init() function. Among other bad effects, this causes the
OMAP hwmod layer to oops on boot.
Thanks to Carlos Aguiar <carlos.aguiar@indt.org.br> and Stefano
Panella <Stefano.Panella@csr.com> for reporting this bug. Thanks to Tony
Lindgren <tony@atomide.com> for N800 booting advice.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Carlos Aguiar <carlos.aguiar@indt.org.br>
Cc: Stefano Panella <Stefano.Panella@csr.com>
Cc: Tony Lindgren <tony@atomide.com>
There is a possible race condition in clockdomain
code handling hw supported idle transitions.
When multiple autodeps dependencies are being added
or removed, a transition of still remaining dependent
powerdomain can result in false readings of the
state counter. This is especially fatal for off mode
state counter, as it could result in a driver not
noticing a context loss.
Fixed by disabling hw supported state transitions
when autodeps are being changed.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch initializes the correct SDRC settings required
for DVFS on Zoom2.
Signed-off-by: Teerth Reddy <teerth@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The I2C-1 bus frequency on RX-51 should be 2.2 MHz. The speed is limited
by TWL5030/GAIA; a higher speed could lead to errors on the interface. The
maximum speed depends on the system clock for GAIA: 2.2 MHz (if 19.2 MHz),
2.4 MHz (26 MHz) or 2.9 MHz (38.4 MHz).
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The original driver was written with the KEY() macro defined as (col,
row) instead of (row, col) as defined by the matrix keypad
infrastructure. So the keymap was defined accordingly. Since the
driver that was merged upstream uses the matrix keypad infrastructure,
modify the keymap accordingly.
While we are at it, fix the comments in twl4030.h and define
PERSISTENT_KEY as (r,c) instead of (c, r)
Tested on a RX51 (N900) device.
Signed-off-by: Amit Kucheria <amit.kucheria@verdurent.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and
USBTLL f-clock are the only users of this DPLL, and 120MHz is
is the only recommended rate for these clocks.
With this patch, the 60 MHz ULPI clock is generated correctly.
Tested on an OMAP3430 SDP.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The 'pwrdm_for_each()' function walks powerdomains with a spinlock
locked, so the the callbacks cannot do anything which may sleep.
This patch introduces a 'pwrdm_for_each_nolock()' helper which does
the same, but without the spinlock locked. This fixes the following
lockdep warning:
[ 0.000000] WARNING: at kernel/lockdep.c:2460 lockdep_trace_alloc+0xac/0xec()
[ 0.000000] Modules linked in:
(unwind_backtrace+0x0/0xdc) from [<c0045464>] (warn_slowpath_common+0x48/0x60)
(warn_slowpath_common+0x48/0x60) from [<c0067dd4>] (lockdep_trace_alloc+0xac/0xec)
(lockdep_trace_alloc+0xac/0xec) from [<c009da14>] (kmem_cache_alloc+0x1c/0xd0)
(kmem_cache_alloc+0x1c/0xd0) from [<c00b21d8>] (d_alloc+0x1c/0x1a4)
(d_alloc+0x1c/0x1a4) from [<c00a887c>] (__lookup_hash+0xd8/0x118)
(__lookup_hash+0xd8/0x118) from [<c00a9f20>] (lookup_one_len+0x84/0x94)
(lookup_one_len+0x84/0x94) from [<c010d12c>] (debugfs_create_file+0x8c/0x20c)
(debugfs_create_file+0x8c/0x20c) from [<c010d320>] (debugfs_create_dir+0x1c/0x20)
(debugfs_create_dir+0x1c/0x20) from [<c000e8cc>] (pwrdms_setup+0x60/0x90)
(pwrdms_setup+0x60/0x90) from [<c002e010>] (pwrdm_for_each+0x30/0x80)
(pwrdm_for_each+0x30/0x80) from [<c000e79c>] (pm_dbg_init+0x7c/0x14c)
(pm_dbg_init+0x7c/0x14c) from [<c00232b4>] (do_one_initcall+0x5c/0x1b8)
(do_one_initcall+0x5c/0x1b8) from [<c00083f8>] (kernel_init+0x90/0x10c)
(kernel_init+0x90/0x10c) from [<c00242c4>] (kernel_thread_exit+0x0/0x8)
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
USBHOST module has 2 fclocks (for HOST1 and HOST2), only one iclock
and only a single bit in the WKST register to indicate a wakeup event.
Because of the single WKST bit, we cannot know whether a wakeup event
was on HOST1 or HOST2, so enable both fclocks before clearing the
wakeup event to ensure both hosts can properly clear the event.
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Clearing wakeup sources is now only done when the PRM indicates a
wakeup source interrupt. Since we don't handle any other types of
PRCM interrupts right now, warn if we get any other type of PRCM
interrupt. Either code needs to be added to the PRCM interrupt
handler to react to these, or these other interrupts should be masked
off at init.
Updated after Jon Hunter's PRCM IRQ rework by Kevin Hilman.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
PM_WKST register contents should be ANDed with the contents of the
MPUGRPSEL registers. Otherwise the MPU PRCM interrupt handler could
wind up clearing wakeup events meant for the IVA PRCM interrupt
handler. A future revision to this code should be to read a cached
version of MPUGRPSEL from the powerdomain code, since PRM reads are
relatively slow.
Updated after Jon Hunter's PRCM IRQ change by Kevin Hilman
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
There are two scenarios where a race condition could result in a hang
in the prcm_interrupt handler. These are:
1). Waiting for PRM_IRQSTATUS_MPU register to clear.
Bit 0 of the PRM_IRQSTATUS_MPU register indicates that a wake-up event
is pending for the MPU. This bit can only be cleared if the all the
wake-up events latched in the various PM_WKST_x registers have been
cleared. If a wake-up event occurred during the processing of the prcm
interrupt handler, after the corresponding PM_WKST_x register was
checked but before the PRM_IRQSTATUS_MPU was cleared, then the CPU
would be stuck forever waiting for bit 0 in PRM_IRQSTATUS_MPU to be
cleared.
2). Waiting for the PM_WKST_x register to clear.
Some power domains have more than one wake-up source. The PM_WKST_x
registers indicate the source of a wake-up event and need to be cleared
after a wake-up event occurs. When the PM_WKST_x registers are read and
before they are cleared, it is possible that another wake-up event
could occur causing another bit to be set in one of the PM_WKST_x
registers. If this did occur after reading a PM_WKST_x register then
the CPU would miss this event and get stuck forever in a loop waiting
for that PM_WKST_x register to clear.
This patch address the above race conditions that would result in a
hang.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
It's worked fine so far since reset is done for the first time.
Reported-by: Juha Leppanen <juha_motorsportcom@luukku.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Juha Leppanen <juha_motorsportcom@luukku.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Earlier BeagleBoards were using pad AH8 muxed to GPIO29 for MMC write-protect.
However, this signal has been changed to pad AG9 in board revision C2.
Fix this by adding mux configuration for pad AG9, runtime check for board
revisions and set the gpio number and pad muxing accordingly.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The only way to flush posted write to L4 bus is to do a read back
of the same register right after the write.
This seems to be mostly needed in interrupt handlers to avoid
causing spurious interrupts.
The earlier fix has been to mark the L4 bus as strongly ordered
memory, which solves the problem, but causes performance penalties.
Similar to the fix, 03803a71041e3bc3c077f4e7b92f6ceaa9426df3
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The softreset at startup is introduced as TRM describes and also some
register bit definitions are added instead of magic number.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPIO135 is used as EHCI (port2) phy reset pin on Multi Media Daughter card
connected to OMAP3EVM.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Patch 941132606c split IO_ADDRESS
into OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS except for the omap4
code to avoid merge conflicts with the omap4 code that was queued
earlier.
Signed-off-by: Tony Lindgren <tony@atomide.com>
* git://git.infradead.org/mtd-2.6: (58 commits)
mtd: jedec_probe: add PSD4256G6V id
mtd: OneNand support for Nomadik 8815 SoC (on NHK8815 board)
mtd: nand: driver for Nomadik 8815 SoC (on NHK8815 board)
m25p80: Add Spansion S25FL129P serial flashes
jffs2: Use SLAB_HWCACHE_ALIGN for jffs2_raw_{dirent,inode} slabs
mtd: sh_flctl: register sh_flctl using platform_driver_probe()
mtd: nand: txx9ndfmc: transfer 512 byte at a time if possible
mtd: nand: fix tmio_nand ecc correction
mtd: nand: add __nand_correct_data helper function
mtd: cfi_cmdset_0002: add 0xFF intolerance for M29W128G
mtd: inftl: fix fold chain block number
mtd: jedec: fix compilation problem with I28F640C3B definition
mtd: nand: fix ECC Correction bug for SMC ordering for NDFC driver
mtd: ofpart: Check availability of reg property instead of name property
driver/Makefile: Initialize "mtd" and "spi" before "net"
mtd: omap: adding DMA mode support in nand prefetch/post-write
mtd: omap: add support for nand prefetch-read and post-write
mtd: add nand support for w90p910 (v2)
mtd: maps: add mtd-ram support to physmap_of
mtd: pxa3xx_nand: add single-bit error corrections reporting
...
tAdd adds McSPI support for OMAP4430 SDP platform. All the base addresses
are changed between OMAP1/2/3 and OMAP4. The fields of the resource
structures are filled at runtime to have McSPI support on OMAP4.
Signed-off-by: Syed Rafiuddin <rafiuddin.syed@ti.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add basic support for all 5 MMC controllers on OMAP4.
This patch doesn't include mmc-regulator support
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Acked-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Cc: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Specify MMC capabilities and set the power-saving flag for RX51.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Cc: Denis Karpov <ext-denis.2.karpov@nokia.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Philip Langdale <philipl@overt.org>
Cc: "Madhusudhan" <madhu.cr@ti.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add the ability for the driver to put the card power regulators to sleep
and wake them up again.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Cc: Denis Karpov <ext-denis.2.karpov@nokia.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Philip Langdale <philipl@overt.org>
Cc: "Madhusudhan" <madhu.cr@ti.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Support for multi-level dynamic power saving states in omap_hsmmc
(ENABLED->DISABLED->OFF). In the "deepest" state (OFF) we switch off the
voltage regulators.
Signed-off-by: Denis Karpov <ext-denis.2.karpov@nokia.com>
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Cc: Denis Karpov <ext-denis.2.karpov@nokia.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Philip Langdale <philipl@overt.org>
Cc: "Madhusudhan" <madhu.cr@ti.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Let the board specify that a card is nonremovable e.g. eMMC
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Cc: Denis Karpov <ext-denis.2.karpov@nokia.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Philip Langdale <philipl@overt.org>
Cc: "Madhusudhan" <madhu.cr@ti.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
PM dynamic OFF state results in context loss. That is, the host
controller has been powered off at some point, which means the registers
have been reset. The driver must detect when this happens, and restore
the context. This patch adds the means to detect context loss.
Note, the PM side is not yet implemented.
Signed-off-by: Denis Karpov <ext-denis.2.karpov@nokia.com>
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com>
Cc: Denis Karpov <ext-denis.2.karpov@nokia.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Philip Langdale <philipl@overt.org>
Cc: "Madhusudhan" <madhu.cr@ti.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch adds prefetch support to access nand flash in mpu mode.
This patch also adds 8-bit nand support (omap_read/write_buf8).
Prefetch can be used for both 8- and 16-bit devices.
Signed-off-by: Vimal Singh <vimalsingh@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Remove the ARM dependency from the generic "onenand" platform device
driver. This change makes the driver useful for other architectures as
well. Needed for the SuperH kfr2r09 board.
Apart from the obvious Kconfig bits, the most important change is the move
away from ARM specific includes and platform data. Together with this
change the only in-tree board code gets an update, and the driver name is
also changed gracefully break potential out of tree drivers.
The driver is also updated to allow NULL as platform data together with a
few changes to make use of resource_size() and dev_name().
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kyungmin Park <kmpark@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add support for Dynamic Power Switching (DPS) for the RX51 board.
These scripts are still a work-in-progress. I'll keep sending patches to
update the scripts as they are optimised.
Signed-off-by: Amit Kucheria <amit.kucheria@verdurent.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
[ARM] Update mach-types
ARM: 5636/1: Move vendor enum to AMBA include
ARM: Fix pfn_valid() for sparse memory
[ARM] orion5x: Add LaCie NAS 2Big Network support
[ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
ARM: 5689/1: Update default config of HP Jornada 700-series machines
ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
ARM: 5688/1: ks8695_serial: disable_irq() lockup
ARM: 5687/1: fix an oops with highmem
ARM: 5684/1: Add nuc960 platform to w90x900
ARM: 5683/1: Add nuc950 platform to w90x900
ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
MMC: MMCI: convert realview MMC to use gpiolib
ARM: 5685/1: Make MMCI driver compile without gpiolib
ARM: implement highpte
ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
...
Fix up trivial conflict in arch/arm/kernel/signal.c.
It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.
* topic/asoc: (226 commits)
ASoC: au1x: PSC-AC97 bugfixes
ASoC: Fix WM835x Out4 capture enumeration
ASoC: Remove unuused hw_read_t
ASoC: fix pxa2xx-ac97.c breakage
ASoC: Fully specify DC servo bits to update in wm_hubs
ASoC: Debugged improper setting of PLL fields in WM8580 driver
ASoC: new board driver to connect bfin-5xx with ad1836 codec
ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI
ASoC: davinci: i2c device creation moved into board files
ASoC: Don't reconfigure WM8350 FLL if not needed
ASoC: Fix s3c-i2s-v2 build
ASoC: Make platform data optional for TLV320AIC3x
ASoC: Add S3C24xx dependencies for Simtec machines
ASoC: SDP3430: Fix TWL GPIO6 pin mux request
ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time
ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop
ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
OMAP: McBSP: Use textual values in DMA operating mode sysfs files
ARM: OMAP: DMA: Add support for DMA channel self linking on OMAP1510
ASoC: Select core DMA when building for S3C64xx
...
Connect the omap_hwmod code to the kernel boot. Create some basic
interconnect and device structures for OMAP2/3 chips.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP SoCs can be considered a collection of hardware IP blocks
connected by various interconnects. The bus topology and device
integration data is somewhat more complex than platform_device can
encode. This patch creates code and structures to manage information
about OMAP on-chip devices ("hardware modules") and their integration
to the rest of the chip. Hardware module data is intended to be
generated dynamically from the TI hardware database for the OMAP4
chips and beyond, easing Linux support for new chip variants.
This code currently:
- resets and configures all hardware modules upon startup, reducing bootloader
dependencies;
- provides hooks for Linux driver model code to enable, idle, and shutdown
hardware modules (forthcoming patch);
- waits for hardware modules to leave idle once their clocks
are enabled and OCP_SYSCONFIG bits are set appropriately.
- provides a means to pass arbitrary IP block configuration data (e.g.,
FIFO size) to the device driver (via the dev_attr void pointer)
In the future this code is intended to:
- estimate interconnect bandwidth and latency characteristics to
ensure constraints are satisfied during DVFS
- provide *GRPSEL bit data to the powerdomain code
- handle pin/ball muxing for devices
- generate IO mapping information dynamically
- supply device firewall configuration data
- provide hardware module data to other on-chip coprocessor software
- allow the removal of the "disable unused clocks" code in the OMAP2/3
clock code
This patch represents a collaborative effort involving many people from TI,
Nokia, and the Linux-OMAP community.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Sakari Poussa <sakari.poussa@nokia.com>
Cc: Anand Sawant <sawant@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Eric Thomas <ethomas@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Most board-*.c files read configuration data from the bootloader in
their .init_machine() function. This needs to happen earlier, at some
point before omap2_init_common_hw() is called. This is because a
future patch will use the bootloader serial console port information
to enable the UART clocks earlier, immediately after omap2_clk_init().
This is in turn necessary since otherwise clock tree usecounts on
clocks like dpll4_m2x2_ck will be bogus, which can cause the
currently-active console UART clock to be disabled during boot.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
After a hardware module's clocks are enabled, Linux must wait for it
to indicate readiness via its IDLEST bit before attempting to access
the device, otherwise register accesses to the device may trigger an
abort. This has traditionally been implemented in the clock
framework, but this is the wrong place for it: the clock framework
doesn't know which module clocks must be enabled for a module to leave
idle; and if a module is not in smart-idle mode, it may never leave
idle at all. This type of information is best stored in a
per-hardware module data structure (coming in a following patch),
rather than a per-clock data structure. The new code will use these new
functions to handle waiting for modules to enable.
Once hardware module data is filled in for all of the on-chip devices,
the clock framework code to handle IDLEST waiting can be removed.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The interface provides device drivers, CPUFreq, and DSPBridge with a
means of controlling OMAP power management parameters that are not yet
supported by the Linux PM PMQoS interface. Copious documentation is
in the patch in Documentation/arm/OMAP/omap_pm and the interface
header file, arch/arm/plat-omap/include/mach/omap-pm.h.
Thanks to Rajendra Nayak <rnayak@ti.com> for adding CORE (VDD2) OPP
support and moving the OPP table initialization earlier in the event
that the clock code needs them. Thanks to Tero Kristo
<tero.kristo@nokia.com> for fixing the parameter check in
omap_pm_set_min_bus_tput(). Jouni signed off on Tero's patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Jouni Högander <jouni.hogander@nokia.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Igor Stoppa <igor.stoppa@nokia.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Anand Sawant <sawant@ti.com>
Cc: Sakari Poussa <sakari.poussa@nokia.com>
Cc: Veeramanikandan Raju <veera@ti.com>
Cc: Karthik Dasu <karthik-dp@ti.com>
omap2_init_clk_clkdm() is called as part of the chip architecture-specific
initialization code, so calling it again from the struct clk init pointer
just wastes cycles.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
All MPU-related clocks should be in the mpu_clkdm. This is needed for the
upcoming omap_hwmod patches, which needs to know the clockdomain that arm_fck
is in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The argument 'mpurate' had no effect on the MPU
frequency. This patch fixes the same.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
At the end of the list pd is a pointer to a NULL struct, so checking
if the address == NULL doesn't help here. In fact the original code
will just keep running past the struct to read who knows what in
memory.
This case manifests itself when from clkdms_setup() when enabling auto
idle for a clock domain and the clockdomain usecount is greater than
0. When _clkdm_add_autodeps() tries to add the a dependency that does
not exist in the powerdomain->wkdep_srcs array the for loop will run
past the wkdep_srcs array.
Currently in linux-omap you won't hit this because the not found case
is never executed, unless you start modifying powerdomains and their
wakeup/sleep deps.
Signed-off-by: Mike Chan <mike@android.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Target state can be read / programmed via files under:
[debugfs]/pm_debug/[pwrdm]/suspend
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Allows dumping out current register contents from the debug filesystem, and
also allows user to add arbitrary register save points into code. Current
register contents are available under debugfs at:
[debugfs]/pm_debug/registers/current
To add a save point, do following:
From module init (or somewhere before the save call, called only once):
pm_dbg_init_regset(n); // n=1..4, allocates memory for dump area #n
From arbitrary code location:
pm_dbg_regset_save(n); // n=1..4, saves registers to dump area #n
After this, the register dump can be seen under [debugfs]/pm_debug/registers/n
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Make the powerdomain code call the new hook for updating the time.
Also implement the updated pwrdm_for_each.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch provides the debugfs entries and a function which will be
called by the PM code to register the time spent per domain per
state. Also some new fields are added to the powerdomain struct to
keep the time information.
NOTE: As of v2.6.29, using getnstimeofday() after drivers are
suspended is no longer safe since the timekeeping subsystem is also
suspended as part of the suspend process. Instead use sched_clock()
which on OMAP returns the 32k SYNC timer in nanoseconds.
Also, do not print out status for meta powerdomains (dpll*)
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add some infrastructure to easily iterate over clock and power
domains.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch modifies the clock, clockdomain and OMAP3 specific
powerdomain code to call the PM counter infrastructure whenever one or
more powerdomains might have changed state.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch provides the infrastructure to count how many times a
powerdomain entered a given power state (on, inactive, retention,
off). A number of functions are provided which will be called by the
chip specific powerdomain and clockdomain code whenever a transition
might have happened.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch uses kmalloc(size,GFP_ATOMIC) instead of kmalloc(size,GFP_KERNEL)
to allocate memory for instance of struct power_state in pwrdms_setup(),
since it may be called by pwrdm_for_each() with irq disabled.
It is a easy fix for the following lockdep warning caused by
kmalloc(size,GFP_KERNEL) in pwrdms_setup():
Power Management for TI OMAP3.
------------[ cut here ]------------
WARNING: at kernel/lockdep.c:2282 lockdep_trace_alloc+0xe8/0xfc()
Modules linked in:
[<c0032ccc>] (unwind_backtrace+0x0/0xec) from [<c0056934>] (warn_slowpath_common+0x48/0x60)
[<c0056934>] (warn_slowpath_common+0x48/0x60) from [<c007da10>] (lockdep_trace_alloc+0xe8/0xfc)
[<c007da10>] (lockdep_trace_alloc+0xe8/0xfc) from [<c00cd9bc>] (kmem_cache_alloc+0x28/0x178)
[<c00cd9bc>] (kmem_cache_alloc+0x28/0x178) from [<c000f184>] (pwrdms_setup+0x30/0xf8)
[<c000f184>] (pwrdms_setup+0x30/0xf8) from [<c00381c4>] (pwrdm_for_each+0x64/0x84)
[<c00381c4>] (pwrdm_for_each+0x64/0x84) from [<c000ef60>] (omap3_pm_init+0x3f4/0x5ac)
[<c000ef60>] (omap3_pm_init+0x3f4/0x5ac) from [<c002c2c0>] (do_one_initcall+0x30/0x1d4)
[<c002c2c0>] (do_one_initcall+0x30/0x1d4) from [<c00088d8>] (kernel_init+0xa4/0x118)
[<c00088d8>] (kernel_init+0xa4/0x118) from [<c002ddf8>] (kernel_thread_exit+0x0/0x8)
---[ end trace 1e06f8d97dc5a19b ]---
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Release the Dbg board detection gpio once its purpose is served
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch changes for setting the padconf value for sys_nirq line
which is connected to T2 INTR1. This will fix the T2 keypad wakeup
issue on OMAP3 SDP.
Signed-off-by: Teerth Reddy <teerth@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
In usb_musb_pm_init, we attempt to access an MUSB register
when the i-clock may not be on, or the module is otherwise
not accessible.
We need to either:
- enable the clock before this access, or
- remove this code and move it to the bootloader, or
- enable the clock in the bootloader
If we enable the clock in the bootloader, we might as well
add the workaround in the bootloader itself. This code will
anyway be changed once hwmod is in place, so remove it for now
This allows us to boot the kernel on certain OMAP3 boards with
a bootloader that doesn't enable this clock. Without this, we
will need to upgrade the bootloaders on these boards.
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Now that on-chip UARTs each have separate platform_data, the external
UART needs an non-conflicting ID. Since there are 3 on-chip UARTs,
the Zoom2 external UART will be registered after as the fourth.
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Second reason of OMAP4 boot failure on 2.6.31.rc6, the UART
platform data is not getting registered to kernel.
Registration was failing because of clock check failure in
omap_serial_init().
Below patch fix the same.
OMAP4 clock framework patches are still getting discussed on mailing
list so till then we need this.
Signed-off-by: Syed Rafiuddin <rafiuddin.syed@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
After the patch series "[PATCH 00/14] OMAP PM fixes for .31-rc"
merge in 2.6.31-rc5, the kernel crashed during boot on OMAP4430.
This patch fixes it by adding UART4 support and related code.
Without this patch omap_serial_init() would produce " NULL pointer
dereference" and kernel crashes in the bootup on OMAP4430 platform.
Some more info on the merge issue can be found here.
More info- http://lkml.org/lkml/2009/8/20/192
Note: While merging this patch,"IO_ADDRESS" needs to be changed
to "OMAP2_IO_ADDRESS" if the Tony's below series is already merged in.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg15072.html
Signed-off-by: Syed Rafiuddin <rafiuddin.syed@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
For OMAP3 add MMC1 MMC2 pin mux MMC3 mux is not added as there are
multiple configurations possible, so the muxing is left to be done
in board file.
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Chikkature Rajashekar <madhu.cr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This enables to peek the following data.
$ /debug/iommu/isp# ls
mem nr_tlb_entries regs
mmap pagetable tlb
$ /debug/iommu/isp# head pagetable
L: da: pa:
-----------------------------------------
2: 00001000 8ae4a002
2: 00002000 8e7bb002
2: 00003000 8ae49002
2: 00004000 8ae65002
.....
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add board file for Nokia N800 and N810 devices. Currently only serial ports,
onenand and spi are configured, more to come later.
Tested on Nokia N800.
Signed-off-by: Kalle Valo <kalle.valo@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For some reason usb-tusb6010.c was't compiled, add it to Makefile and
Kconfig. This is prepraration for upcoming n8x0 support.
Signed-off-by: Kalle Valo <kalle.valo@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP tags are deprecrated so drop them.
Drop UART config data which decides which UARTs to enable during boot.
This is no longer necessary since serial core code disables clocks
after inactivity.
Background: with new UART idle code, all on-chip UARTs are idled using
a configurable inactivity timer (default 5 seconds.) After the
inactivity timer, UART clocks are disabled automatically.
Signed-off-by: Kalle Valo <kalle.valo@iki.fi>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Search and replace OMAP_IO_ADDRESS with OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS,
and convert omap_read/write into a functions instead of a macros.
Also rename OMAP_MPUIO_VBASE to OMAP1_MPUIO_VBASE.
In the long run, most code should use ioremap + __raw_read/write instead.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Do not allow applications to use the full buffer found on
McBSP1,3,4,5. Using the full buffer in threshold mode causes
the McBSP buffer to run dry, which can be observed as channels
are switching (in reality the channels are shifting).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch export through sysfs two properties to configure
maximum threshold for transmission and reception on each
mcbsp instance. Also, it exports two helper functions to
allow mcbsp users to read this values.
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
twl_mmc_cleanup() must free up the regulators that were
allocated by twl_mmc_late_init().
This eliminates the below error when 'omap_hsmmc' module is
repeatedly loaded and unloaded.
"sysfs: cannot create duplicate filename '/devices/platform
/mmci-omap-hs.0/microamps_requested_vmmc'"
Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add OTG transceiver to RX51 platform data to prevent kernel NULL pointer
dereference during MUSB initialisation.
Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fixes a wrong setting of resource parameter list in
SMSC911x platform driver data structure for Overo case.
This fixes folowing warning when compiling for Overo board:
warning: initialization from incompatible pointer type
Introduced since commit id:
commit 172ef27544
Author: Steve Sakoman <sakoman@gmail.com>
Date: Mon Feb 2 06:27:49 2009 +0000
ARM: Add SMSC911X support to Overo platform (V2)
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP3EVM uses ISP1504 phy which doesn't require any programming and
thus has to use NOP otg transceiver.
Cleanups being done:
- Remove unwanted code in usb-musb.c file
- Register NOP in OMAP3EVM board file using
usb_nop_xceiv_register().
- Select NOP_USB_XCEIV for OMAP3EVM boards.
- Don't enable TWL4030_USB in omap3_evm_defconfig
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Eino-Ville Talvala <talvala@stanford.edu>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Powerdomain previous state is checked after restoring new states in
suspend. This patch fixes this problem.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Use list_add_tail() when adding discovered UART ports. This is so
traversal using list_for_each_entry() will traverse the list in the
order they were found.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch causes the OMAP uarts to honor the sysfs power/wakeup file
for IOPAD wakeups. Before the OMAP was always woken up from off mode
on a rs232 signal change. This patch also creates a different
platform device for each serial port so that the wakeup properties can
be control per port.
By default, IOPAD wakeups are enabled for each UART. To disable,
# echo disabled > /sys/devices/platform/serial8250.0/power/wakeup
Where serial8250.0 can be replaced by .1, or .2 to control the other
ports.
Original idea and original patch from Russ Dill <russ.dill@gmail.com>
Cc: Russ Dill <russ.dill@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
It was possible for an unhandled interrupt to occur if there was incoming
serial traffic during wakeup from suspend. This was caused by the code
in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time,
but not acking its interrupts. Applies on top of PM branch.
Use the PM begin/end hooks to ensure that the "serial idle" interrupts
are disabled during the suspend path. Also, since begin/end hooks are
now used, use the suspend_state that is passed in the begin hook instead
of the enter hook as per the platform_suspend_ops docs.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Streamline the OMAP4 special IRQ assignments by putting inside
normal init loop instead of having a separate loop.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
By default, prevent functional wakeups from inside a module from
waking up the IVA2. Let DSP Bridge code handle this when loaded.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch creates McBSP support on OMAP4430 development platform. This patch
includes corresponding base address changes for OMAP4.
Signed-off-by: Syed Rafiuddin <rafiuddin.syed@ti.com>
fix the following 'make includecheck' warning:
arch/arm/mach-omap2/mcbsp.c: mach/irqs.h is included more than once.
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Acked-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits
are in CM_{I,F}CLKEN2_CORE [1]. Fix by implementing a custom clkops
.find_idlest function to return the correct slave IDLEST register.
...
1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1
(Rev. V) Technical Reference Manual, tables 4-99 and 4-105.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not
handled by the current omap2_wait_clock_ready() code. In preparation
for patches that fix the unusual devices, rename the function
omap2_wait_clock_ready() to omap2_wait_module_ready() and split it
into three parts:
1. A clkops-specific companion clock return function (by default,
omap2_clk_dflt_find_companion())
2. A clkops-specific CM_IDLEST register address and bit shift return
function (by default, omap2_clk_dflt_find_idlest())
3. Code to wait for the CM to indicate that the module is ready
(omap2_cm_wait_idlest())
Clocks can now specify their own custom find_companion() and find_idlest()
functions; used in subsequent patches.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The clock stabilization delay post a M2 divider change is needed
even before a SDRC interface clock re-enable and not only before
jumping back to SDRAM.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze. The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.
Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum
(34xx erratum 1.150) that can cause memory corruption if PWDENA is
enabled.
Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>.
Tested on BeagleBoard rev C2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
This patches ensures the MUX settings are correct for the SDRC
CKE signals to SDRAM. This allows the self-refresh to work when
2 chip-selects are in use.
A warning is thrown away in case the initial muxing is incorrect,
in order to track faulty or old-dated bootloaders.
Note: The CONFIG_OMAP_MUX and CONFIG_OMAP_MUX_WARNINGS options
must be enabled for the mux code to have effect.
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.
This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS
Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers
Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Use async timings when sync timings are not requested.
Also ensure that OneNAND is in async mode when async
timings are used.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The omap_type() function is added and returns the DEVICETYPE field of
the CONTROL_STATUS register. The result can be used for conditional
code based on whether device is GP (general purpose), EMU or
HS (high security). Also move the type defines so omap1 code
compile does not require ifdefs for sections using these defines.
This code is needed for the following fix to set the SRAM
size correctly for HS omaps. Also at least PM and watchdog
code will need this function.
Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq
is unsigned, so the error was not noticed.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which
breaks MMC3. Find the right controller to use instead.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1
after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Correspondence with the TI OMAP hardware team indicates that
SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number
was apparently derived from process validation. This is only used
when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
83MHz).
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430
SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC
with GIC used for interrupt handling and SCU for cache coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
