Commit graph

21 commits

Author SHA1 Message Date
Russell King
f4117ac9e2 ARM: P2V: separate PHYS_OFFSET from platform definitions
This uncouple PHYS_OFFSET from the platform definitions, thereby
facilitating run-time computation of the physical memory offset.

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Magnus Damm <damm@opensource.se>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Wan ZongShun <mcuos.com@gmail.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Eric Miao <eric.y.miao@gmail.com>
Acked-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-17 23:26:55 +00:00
Russell King
404a02cbd2 Merge branch 'devel-stable' into devel
Conflicts:
	arch/arm/mach-pxa/clock.c
	arch/arm/mach-pxa/clock.h
2011-01-06 22:33:32 +00:00
Russell King
4073723acb Merge branch 'misc' into devel
Conflicts:
	arch/arm/Kconfig
	arch/arm/common/Makefile
	arch/arm/kernel/Makefile
	arch/arm/kernel/smp.c
2011-01-06 22:32:52 +00:00
Russell King
50401d77ee Merge branch 'master' of git://git.infradead.org/users/cbou/linux-cns3xxx into devel-stable 2011-01-03 10:31:38 +00:00
Russell King
7627dc802a ARM: GIC: private a standard get_irqnr_preamble assembler macro
Provide a standard get_irqnr_preamble assembler macro for platforms
to use, which retrieves the base address of the GIC CPU interface
from gic_cpu_base_addr.  Allow platforms to override this by defining
HAVE_GET_IRQNR_PREAMBLE.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:47 +00:00
Russell King
ff2e27ae0b ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:42 +00:00
Russell King
b580b899dd ARM: GIC: provide a single initialization function for boot CPU
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:30 +00:00
Magnus Damm
960351fb8e ARM: 6476/1: Use shared GIC entry macros on CNS3XXX
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the CNS3XXX subarchitecture.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-07 09:20:24 +00:00
Hans Ulli Kroll
0b05da7200 ARM: 6520/1: Kconfig: add new symbol MIGHT_HAVE_PCI
Today more boards with arm cpu have selectable pci bus.
This patch makes this more scalable and remove line continuations in
Kconfig

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-05 08:39:30 +00:00
Anton Vorontsov
44266416f7 ARM: cns3xxx: Fix build with CONFIG_PCI=y
commit 6338a6aa7c ("ARM: 6269/1: Add 'code'
parameter for hook_fault_code()") breaks CNS3xxx build:

  CC      arch/arm/mach-cns3xxx/pcie.o
pcie.c: In function 'cns3xxx_pcie_init':
pcie.c:373: warning: passing argument 4 of 'hook_fault_code' makes integer from pointer without a cast
pcie.c:373: error: too few arguments to function 'hook_fault_code'

This commit fixes the small issue.

Cc: stable@kernel.org [36]
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2010-11-29 19:19:15 +03:00
Mac Lin
cf36797f35 ARM: cns3xxx: Add architecture definition for EHCI/OHCI controller
This patch add plateform_device for EHCI and OHCI controller on CNS3XXX.
Power reference count (usb_pwr_ref) is used to control enabling and
disabling the single clock control for both EHCI and OHCI controller.

It also removes EHCI/OHCI unused virtual address definitions.

Signed-off-by: Mac Lin <mkl0301@gmail.com>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2010-11-26 21:10:51 +03:00
Mac Lin
38e64ba0f1 ARM: cns3xxx: Add new and export the old power management functions
This patch adds cns3xxx_pwr_clk_dis, and exports these power management
functions that may be used by many other device drivers on CNS3XXX.

Signed-off-by: Mac Lin <mkl0301@gmail.com>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2010-11-26 21:10:50 +03:00
Anton Vorontsov
df8f4d2f3e ARM: cns3xxx: Make cns3xxx_pwr_soft_rst_force() to actually reset blocks
commit 6eb5d146d4 ("ARM: cns3xxx: Use IO memory accessors everywhere")
breaks cns3xxx_pwr_soft_rst_force() function, so that it doesn't write
cleared bit into the register.

This patch fixes the issue by adding the necessary __raw_writel().

Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2010-11-26 21:10:49 +03:00
Nicolas Pitre
6451d7783b arm: remove machine_desc.io_pg_offst and .phys_io
Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.

The various declarations were removed using the following script:

  grep -rl MACHINE_START arch/arm | xargs \
  sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'

[ Initial patch was from Jeremy Kerr, example script from Russell King ]

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>
2010-10-20 00:27:46 -04:00
Jeremy Kerr
0ea1293009 arm: return both physical and virtual addresses from addruart
Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.

This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.

Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.

Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-10-20 00:27:33 -04:00
Anton Vorontsov
23f5cace4f ARM: cns3xxx: Add support for AHCI controllers
CNS3xxx chips have AHCI-compatible SATA controller. This patch adds
the support using generic ahci_platform driver.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-06-08 17:37:09 +04:00
Anton Vorontsov
6279d0ea92 ARM: cns3xxx: Add support for SDHCI controllers
CNS3xxx chips have SDHCI-compatible SDIO/SD/MMC controller. This patch
adds the support using sdhci-cns3xxx driver.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-06-08 17:37:09 +04:00
Anton Vorontsov
5f32f7a028 ARM: cns3xxx: Add support for PCI Express ports
This patch adds PCIe support for CNS3xxx-based boards. The support
was tested with a directly attached SKY2 NIC, and EHCI USB controller
behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles
work as expected).

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-06-08 17:37:09 +04:00
Anton Vorontsov
6eb5d146d4 ARM: cns3xxx: Use IO memory accessors everywhere
Before it isn't too late let's switch to IO memory accessors.
This patch converts all current _REG users and _REG definitions.
There should be no functional changes.

Suggested-by: Ben Dooks <ben-linux@fluff.org>
Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-06-08 17:31:29 +04:00
Anton Vorontsov
e94cdef039 ARM: cns3xxx: Add CNS3420 Validation Board support
This patch adds support for CNS3420VB rev 1.3 boards. With this patch
CNS3420VB boards are able to boot up to the userspace, with a console
available on UART0.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-05-02 21:55:49 +04:00
Anton Vorontsov
d94f944e10 ARM: cns3xxx: Add basic support for Cavium Networks CNS3xxx processors
This patch adds very basic support for ECONA CNS3xxx ARM11 MPcore
(ARMv6) dual-core processors.

Note that SMP is not yet supported, as well as many peripheral
devices. Support for these features will be added later.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-05-02 21:55:46 +04:00