During validation of the internal clocking setup it has
been found that the following settings were not configured
in an optimal way:
ASRC_CTRL_A: SRCLKDIV was incorrect, instad of divide ratio 3,
ratio of 2 has to be used (as the comment stated)
DAC_CTRL_A: Fs = Fsref is the desired configuration instead of
Fs = Fsref / 1.5
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
To make DSP_A mode working correctly the data delay should be
configured to 0. DSP_B mode thus can not be used with DAC33,
so remove it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Platform data option for the codec to keep the BCLK clock
continuously running in FIFO modes (codec master).
OMAP3 McBSP when in slave mode needs continuous BCLK running
on the serial bus in order to operate correctly.
Since in FIFO mode the DAC33 can also shut down the BCLK clock
and enable it only when it is needed, let the platforms decide
if the CPU side needs the BCLK running or not.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
To avoid race condition especially in FIFO modes the
sequence for enabling and disabling the codec need to
be changed.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
OSCSET calculation was not correct in case of 44.1KHz
sampling rate.
With small adjustment both 48 and 44.1 KHz calculation
now gives the correct value.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In repeated playback the FIFOFLUSH bit remained set, and
never has been cleared.
Clear it during the setup phase.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add possibility to configure the burst mode BCLK divider through platform
data structure.
The BCLK divider changes the actual speed of the serial bus in burst mode,
which is faster than the sampling frequency of the running stream.
In this way platforms can experiment with the optimal burst speed without
the need to modify the codec driver itself.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The BCLK divider was not configured in case of mode7.
This leads to unpredictable behavior when switching between FIFO modes.
Configure the BCLK divider depending on the fifo_mode (FIFO is in use,
or FIFO bypass).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Set the prefill number of samples as the same as the lower
threshold in mode7.
In this way the codec will read the same amount of data on
startup and during the running playback.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The currently available FIFO modes (mode1 and mode7) require master
mode from the codec.
Do not allow the slave configuration when the FIFO is in use.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mode 7 of tlv320dac33 operates in the following way:
The codec is in master mode.
Host configures upper and lower thresholds in tlv320dac33
During playback the codec will clock in the data until the
upper threshold is reached in FIFO. At this point the codec
stops the colocks on the serial bus.
When the FIFO fill is reaching the lower threshold limit the
codec will enable the clocks on the serial bus, and clocks
in data till the upper threshold is reached.
In this mode, we can also request interrupts for threshold
events (upper, lower and alarm), which could be used for
power management.
At this point the interrupts are not enabled for this mode,
but it can be taken into use in the future, when the surrounding
code makes it possible to use it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.oc.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Use switch instead of if statements to configure FIFO bypass
and mode1.
With this change adding new FIFO mode is going to be easier,
and cleaner.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Ensure that the code is going to be readable, when new FIFO modes
are introduced later.
Move the prefill and playback state handling to inlined
functions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In order to have support for more FIFO modes supported by
tlv320dac33, the switch for enabling/disabling the FIFO
use has to be replaced with an enum.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Take the regulator framework in use for managing the power sources.
Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
RT workqueue is going away in the near future, replace it with
singlethread wq for now, which is still supported.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The DAPM widgets are now insntantiated by the core when creating the card
so there is no need for the individual CODEC drivers to do so.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
snd_soc_init_card() is always called as the last part of the CODEC probe
function so we can factor it out into the core card setup rather than
have each CODEC replicate the code to do the initialiastation. This will
be required to support multiple CODECs per card.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Driver for Texas Instruments TLV320DAC33 (SLAS546) low power stereo
audio DAC.
TLV320DAC33 is a stereo audio codec with integrated 24KB FIFO for low
power audio playback.
The digital interface can use I2S, DSP (A or B), Right and Left
justified formats.
DAC33 has stereo analog input, which can be bypassed to the analog
outputs.
Regarding to the internal 24KB FIFO the driver implements 'FIFO bypass'
mode (default) and nSample mode (FIFO is in use).
a) In 'FIFO bypass' mode the internal FIFO is not in use, the codec is
working synchronously as a normal codec (it needs constant stream of
data on the digital interface).
b) The nSample mode implementation uses one interrupt line from DAC33 to
the host:
Alarm threshold is set to 10ms of audio data (limit by the driver
implementation).
DAC33 will signal an interrupt, when the FIFO level goes under the
Alarm threshold.
The host will write to nSample register a value (number of stereo
samples), to tell DAC33 how many samples it should read in a burst from
the host. When the DAC33 received the number of samples, it disables the
clocks on the I2S bus. When the FIFO use again goes under the Alarm
threshold, DAC33 signals the host with an interrupt, and the process is
repeated.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Peter Ujfalusi