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78 commits

Author SHA1 Message Date
Russell King
f00ec48fad ARM: Allow SMP kernels to boot on UP systems
UP systems do not implement all the instructions that SMP systems have,
so in order to boot a SMP kernel on a UP system, we need to rewrite
parts of the kernel.

Do this using an 'alternatives' scheme, where the kernel code and data
is modified prior to initialization to replace the SMP instructions,
thereby rendering the problematical code ineffectual.  We use the linker
to generate a list of 32-bit word locations and their replacement values,
and run through these replacements when we detect a UP system.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04 20:23:36 +01:00
Russell King
7b70c4275f Merge branch 'devel-stable' into devel
Conflicts:
	arch/arm/kernel/entry-armv.S
	arch/arm/kernel/setup.c
	arch/arm/mm/init.c
2010-07-31 14:20:16 +01:00
Russell King
b31fc7af78 Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', 'pl', 'spear' and 'versatile' into devel 2010-07-31 14:19:35 +01:00
Russell King
14764b01a5 Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable 2010-07-21 09:22:45 +01:00
Russell King
ac78884e6d ARM: lockdep: fix unannotated irqs-on
CPU: Testing write buffer coherency: ok
------------[ cut here ]------------
WARNING: at kernel/lockdep.c:3145 check_flags+0xcc/0x1dc()
Modules linked in:
[<c0035120>] (unwind_backtrace+0x0/0xf8) from [<c0355374>] (dump_stack+0x20/0x24)
[<c0355374>] (dump_stack+0x20/0x24) from [<c0060c04>] (warn_slowpath_common+0x58/0x70)
[<c0060c04>] (warn_slowpath_common+0x58/0x70) from [<c0060c3c>] (warn_slowpath_null+0x20/0x24)
[<c0060c3c>] (warn_slowpath_null+0x20/0x24) from [<c008f224>] (check_flags+0xcc/0x1dc)
[<c008f224>] (check_flags+0xcc/0x1dc) from [<c00945dc>] (lock_acquire+0x50/0x140)
[<c00945dc>] (lock_acquire+0x50/0x140) from [<c0358434>] (_raw_spin_lock+0x50/0x88)
[<c0358434>] (_raw_spin_lock+0x50/0x88) from [<c00fd114>] (set_task_comm+0x2c/0x60)
[<c00fd114>] (set_task_comm+0x2c/0x60) from [<c007e184>] (kthreadd+0x30/0x108)
[<c007e184>] (kthreadd+0x30/0x108) from [<c0030104>] (kernel_thread_exit+0x0/0x8)
---[ end trace 1b75b31a2719ed1c ]---
possible reason: unannotated irqs-on.
irq event stamp: 3
hardirqs last  enabled at (2): [<c0059bb0>] finish_task_switch+0x48/0xb0
hardirqs last disabled at (3): [<c002f0b0>] ret_slow_syscall+0xc/0x1c
softirqs last  enabled at (0): [<c005f3e0>] copy_process+0x394/0xe5c
softirqs last disabled at (0): [<(null)>] (null)

Fix this by ensuring that the lockdep interrupt state is manipulated in
the appropriate places.  We essentially treat userspace as an entirely
separate environment which isn't relevant to lockdep (lockdep doesn't
monitor userspace.)  We don't tell lockdep that IRQs will be enabled
in that environment.

Instead, when creating kernel threads (which is a rare event compared
to entering/leaving userspace) we have to update the lockdep state.  Do
this by starting threads with IRQs disabled, and in the kthread helper,
tell lockdep that IRQs are enabled, and enable them.

This provides lockdep with a consistent view of the current IRQ state
in kernel space.

This also revert portions of 0d928b0b61
which didn't fix the problem.

Tested-by: Ming Lei <tom.leiming@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-10 10:53:13 +01:00
Tony Lindgren
f159f4ed55 ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6
The TLS register is only available on ARM1136 r1p0 and later.
Set HWCAP_TLS flags if hardware TLS is available and test for
it if CONFIG_CPU_32v6K is not set for V6.

Note that we set the TLS instruction in __kuser_get_tls
dynamically as suggested by Jamie Lokier <jamie@shareable.org>.

Also the __switch_to code is optimized out in most cases as
suggested by Nicolas Pitre <nico@fluxnic.net>.

Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-09 14:41:35 +01:00
Nicolas Pitre
df0698be14 ARM: stack protector: change the canary value per task
A new random value for the canary is stored in the task struct whenever
a new task is forked.  This is meant to allow for different canary values
per task.  On ARM, GCC expects the canary value to be found in a global
variable called __stack_chk_guard.  So this variable has to be updated
with the value stored in the task struct whenever a task switch occurs.

Because the variable GCC expects is global, this cannot work on SMP
unfortunately.  So, on SMP, the same initial canary value is kept
throughout, making this feature a bit less effective although it is still
useful.

One way to overcome this GCC limitation would be to locate the
__stack_chk_guard variable into a memory page of its own for each CPU,
and then use TLB locking to have each CPU see its own page at the same
virtual address for each of them.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2010-06-14 21:31:01 -04:00
Santosh Shilimkar
124efc27a7 ARM: 6068/1: Fix build break with KPROBES enabled
With CONFIG_KPROBES enabled two section are getting created which
leads to below build break.

LOG:
 AS      arch/arm/kernel/entry-armv.o
arch/arm/kernel/entry-armv.S: Assembler messages:
arch/arm/kernel/entry-armv.S:431: Error: symbol ret_from_exception is in a different section
arch/arm/kernel/entry-armv.S:490: Error: symbol ret_from_exception is in a different section
arch/arm/kernel/entry-armv.S:491: Error: symbol __und_usr_unknown is in a different section

This was introduced by commit 4260415f6a

Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-01 11:32:53 +01:00
Russell King
4260415f6a ARM: fix build error in arch/arm/kernel/process.c
/tmp/ccJ3ssZW.s: Assembler messages:
/tmp/ccJ3ssZW.s:1952: Error: can't resolve `.text' {.text section} - `.LFB1077'

This is caused because:

	.section .data
	.section .text
	.section .text
	.previous

does not return us to the .text section, but the .data section; this
makes use of .previous dangerous if the ordering of previous sections
is not known.

Fix up the other users of .previous; .pushsection and .popsection are
a safer pairing to use than .section and .previous.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-04-21 08:45:21 +01:00
Russell King
7511bce406 ARM: Fix wrong dmb
The __kuser_cmpxchg code uses an ARMv6 dmb instruction, rather than
one based upon the architecture being built for.  Switch to using
the macro provided for this purpose, which also eliminates the
need for an ifdef.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-01-12 18:59:16 +00:00
Russell King
cc20d42986 ARM: Use a definition for the userspace cmpxchg emulation syscall
Use a definition for the cmpxchg SWI instead of hard-coding the number.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
2009-11-10 08:41:12 +00:00
Catalin Marinas
a771fe6e4e ARM: 5757/1: Thumb-2: Correct "mov.w pc, lr" instruction which is unpredictable
The 32-bit wide variant of "mov pc, reg" in Thumb-2 is unpredictable
causing improper handling of the undefined instructions not caught by
the kernel. This patch adds a movw_pc macro for such situations
(currently only used in call_fpe).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-10-14 10:33:05 +01:00
Kirill A. Shutemov
4fb2847437 ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.

Now we have three prefetch abort model:

  * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
  * ARMv6 - provides IFSR, but not IFAR;
  * ARMv7 - provides both IFSR and IFAR.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-10-02 22:34:32 +01:00
Catalin Marinas
83e686ea02 Thumb-2: Correctly handle undefined instructions in the kernel
VFP instructions in the kernel may trigger undefined exceptions if VFP
hardware is not present. This patch corrects the loading of such Thumb-2
instructions. It also marks the "no_fp" label as a function so that the
linker generate a Thumb address.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-09-18 23:30:11 +01:00
Catalin Marinas
200b812d00 Clear the exclusive monitor when returning from an exception
The patch adds a CLREX or dummy STREX to the exception return path. This
is needed because several atomic/locking operations use a pair of
LDREX/STREXEQ and the EQ condition may not always be satisfied. This
would leave the exclusive monitor status set and may cause problems with
atomic/locking operations in the interrupted code.

With this patch, the atomic_set() operation can be a simple STR
instruction (on SMP systems, the global exclusive monitor is cleared by
STR anyway). Clearing the exclusive monitor during context switch is no
longer needed as this is handled by the exception return path anyway.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jamie Lokier <jamie@shareable.org>
2009-09-18 23:30:11 +01:00
Russell King
9b2616c2e8 Merge branch 'for-rmk-2.6.32' of git://git.pengutronix.de/git/ukl/linux-2.6 into devel-stable 2009-08-15 16:51:48 +01:00
Uwe Kleine-König
0d928b0b61 Complete irq tracing support for ARM
Before this patch enabling and disabling irqs in assembler code and by
the hardware wasn't tracked completly.

I had to transpose two instructions in arch/arm/lib/bitops.h because
restore_irqs doesn't preserve the flags with CONFIG_TRACE_IRQFLAGS=y

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-08-13 20:34:37 +02:00
Catalin Marinas
b86040a59f Thumb-2: Implementation of the unified start-up and exceptions code
This patch implements the ARM/Thumb-2 unified kernel start-up and
exception handling code.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-07-24 12:32:54 +01:00
Catalin Marinas
88987ef91b Thumb-2: Add some .align statements to the .S files
Since the Thumb-2 instructions can be 16-bit wide, data in the .text
sections may not be aligned to a 32-bit word and this leads to unaligned
exceptions. This patch does not affect the ARM code generation.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-07-24 12:32:52 +01:00
Russell King
42578c82e0 Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel
Conflicts:
	arch/arm/Kconfig
	arch/arm/kernel/smp.c
	arch/arm/mach-realview/Makefile
	arch/arm/mach-realview/platsmp.c
2009-06-11 15:35:00 +01:00
Catalin Marinas
26584853a4 Add core support for ARMv6/v7 big-endian
Starting with ARMv6, the CPUs support the BE-8 variant of big-endian
(byte-invariant). This patch adds the core support:

- setting of the BE-8 mode via the CPSR.E register for both kernel and
  user threads
- big-endian page table walking
- REV used to rotate instructions read from memory during fault
  processing as they are still little-endian format
- Kconfig and Makefile support for BE-8. The --be8 option must be passed
  to the final linking stage to convert the instructions to
  little-endian

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30 14:00:18 +01:00
Russell King
bac4e960b5 [ARM] barriers: improve xchg, bitops and atomic SMP barriers
Mathieu Desnoyers pointed out that the ARM barriers were lacking:

- cmpxchg, xchg and atomic add return need memory barriers on
  architectures which can reorder the relative order in which memory
  read/writes can be seen between CPUs, which seems to include recent
  ARM architectures. Those barriers are currently missing on ARM.

- test_and_xxx_bit were missing SMP barriers.

So put these barriers in.  Provide separate atomic_add/atomic_sub
operations which do not require barriers.

Reported-Reviewed-and-Acked-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-05-28 19:39:27 +01:00
Catalin Marinas
c4c5716e16 [ARM] 5385/2: unwind: Add unwinding information to exception entry points
This is needed to allow or stop the unwinding at certain points in the
kernel like exception entries.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 11:27:35 +00:00
Russell King
ecbab71c52 [ARM] call undefined instruction exception handler with irqs enabled
Aaro says:
> With spinlock debugs enabled I get might_sleep() warnings when using
> ptrace.

tracked down to a missing enable_irq before calling do_undefinstr().

Reported-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Tested-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-28 10:19:53 +00:00
Catalin Marinas
93ed397011 [ARM] 5227/1: Add the ENDPROC declarations to the .S files
This declaration specifies the "function" type and size for various
assembly functions, mainly needed for generating the correct branch
instructions in Thumb-2.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:34 +01:00
Russell King
a09e64fbc0 [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:55:48 +01:00
Russell King
d1964dab60 Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel 2008-04-19 17:17:25 +01:00
Russell King
28fab1a2fd [ARM] Fix kernel mode preemption
Luc Van Oostenryck reported:

  The code removed by this patch tested the irq_cpustat_t members
  __local_irq_count and __local_bh_count but these fields have
  been removed some time ago:

  http://git.kernel.org/?p=linux/kernel/git/tglx/history.git;a=commitdiff;h=3ab146c93e039dec99fec8d441a8dd046fe510cc

Fix this oversight.

Acked-by:  Bill Gatliff <bgat@billgatliff.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-04-19 11:28:09 +01:00
Paul Brook
cb170a45d6 Linux Thumb-2 support for user-space applications
This patch implements Thumb-2 application support in Linux. Original
implementation by Paul Brook with fixes for VFP and Neon by Catalin
Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:08 +01:00
Paul Brook
48d7927bdf Add a prefetch abort handler
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:07 +01:00
Russell King
d0d42df2a4 Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits)
  [ARM] 4615/4: sam926[13]ek buttons updated
  [ARM] 4765/1: [AT91] AT91CAP9A-DK board support
  [ARM] 4764/1: [AT91] AT91CAP9 core support
  [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
  [ARM] 4761/1: [AT91] Board-support for NEW_LEDs
  [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
  [ARM] 4759/1: [AT91] Buttons on CSB300
  [ARM] 4758/1: [AT91] LEDs
  [ARM] 4757/1: [AT91] UART initialization
  [ARM] 4756/1: [AT91] Makefile cleanup
  [ARM] 4755/1: [AT91] NAND update
  [ARM] 4754/1: [AT91] SSC library support
  [ARM] 4753/1: [AT91] Use DMA_BIT_MASK
  [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
  [ARM] 4751/1: [AT91] ISI peripheral on SAM9263
  [ARM] 4750/1: [AT91] STN LCD displays on SAM9261
  [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
  [ARM] 4646/1: AT91: configurable HZ, default to 128
  [ARM] 4688/1: at91: speed-up irq processing
  [ARM] 4657/1: AT91: Header definition update
  ...

* ep93xx:
  [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
  [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
  [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
  [ARM] 4668/1: ep93xx: implement new GPIO API

* iop:
  [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
  [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
  [ARM] 4708/1: iop: update defconfigs for 2.6.24

* kprobes:
  ARM kprobes: let's enable it
  ARM kprobes: special hook for the kprobes breakpoint handler
  ARM kprobes: prevent some functions involved with kprobes from being probed
  ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
  ARM kprobes: add the kprobes hook to the page fault handler
  ARM kprobes: core code
  ARM kprobes: instruction single-stepping support

* ks8695:
  [ARM] 4603/1: KS8695: debugfs interface to view pin state
  [ARM] 4601/1: KS8695: PCI support

* misc:
  [ARM] remove duplicate includes
  [ARM] CONFIG_DEBUG_STACK_USAGE
  [ARM] 4689/1: small comment wrap fix
  [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
  [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
  [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
  [SERIAL] 21285: Report baud rate back via termios
  [ARM] Remove pointless casts from void pointers,
  [ARM] Misc minor interrupt handler cleanups
  [ARM] Remove at91_lcdc.h
  [ARM] ARRAY_SIZE() cleanup
  [ARM] Update mach-types

* msm:
  [ARM] msm: dma support for MSM7X00A
  [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
  [ARM] msm: irq and timer support for ARCH_MSM7X00A
  [ARM] msm: core platform support for ARCH_MSM7X00A

* s3c2410: (33 commits)
  [ARM] 4795/1: S3C244X: Add armclk and setparent call
  [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
  [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
  [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
  [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
  [ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
  [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
  [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
  [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
  [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
  [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
  [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
  [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
  [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
  [ARM] 4781/1: S3C24XX: DMA suspend and resume support
  [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
  [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
  [ARM] 4778/1: S3C2412: Add armclk and init from DVS state
  [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
  [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
  ...

* sa1100:
  [ARM] sa1100: add clock source support

* vfp:
  [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
  [ARM] 4583/1: ARMv7: Add VFPv3 support
  [ARM] 4582/2: Add support for the common VFP subarchitecture
2008-01-28 13:21:21 +00:00
Nicolas Pitre
785d3cd286 ARM kprobes: prevent some functions involved with kprobes from being probed
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:17 +00:00
Nicolas Pitre
d30a0c8bf9 ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
If kprobes installs a breakpoint on a "stmdb sp!, {...}" instruction,
and then single-step it by simulation from the exception context, it will
corrupt the saved regs on the stack from the previous context.

To avoid this, let's add an optional parameter to the svc_entry macro
allowing for a hole to be created on the stack before saving the
interrupted context, and use it in the undef_svc handler when kprobes
is enabled.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:17 +00:00
Nicolas Pitre
70b6f2b4af [ARM] 4689/1: small comment wrap fix
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 14:50:05 +00:00
Catalin Marinas
b5872db4a2 [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
This patch enables the use of the Advanced SIMD (NEON) extension on
ARMv7. The NEON technology is a 64/128-bit hybrid SIMD architecture
for accelerating the performance of multimedia and signal processing
applications. The extension shares the registers with the VFP unit and
enabling/disabling and saving/restoring follow the same rules. In
addition, there are instructions that do not have the appropriate CP
number encoded, the checks being made in the call_fpe function.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 14:44:02 +00:00
Nicolas Pitre
d28a170d5b [ARM] 4665/1: fix __und_usr wrt accessing the undefined insn in user space
The ldrt fixup code expects r9 to be set.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-11-26 19:44:02 +00:00
Nicolas Pitre
b49c0f24cf [ARM] 4659/1: remove possibilities for spurious false negative with __kuser_cmpxchg
The ARM __kuser_cmpxchg routine is meant to implement an atomic cmpxchg
in user space.  It however can produce spurious false negative if a
processor exception occurs in the middle of the operation.  Normally
this is not a problem since cmpxchg is typically called in a loop until
it succeeds to implement an atomic increment for example.

Some use cases which don't involve a loop require that the operation be
100% reliable though.  This patch changes the implementation so to
reattempt the operation after an exception has occurred in the critical
section rather than abort it.

Here's a simple program to test the fix (don't use CONFIG_NO_HZ in your
kernel as this depends on a sufficiently high interrupt rate):

	#include <stdio.h>

	typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
	#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)

	int main()
	{
		int i, x = 0;
		for (i = 0; i < 100000000; i++) {
			int v = x;
			if (__kernel_cmpxchg(v, v+1, &x))
				printf("failed at %d: %d vs %d\n", i, v, x);
		}
		printf("done with %d vs %d\n", i, x);
		return 0;
	}

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-11-26 19:43:58 +00:00
Dan Williams
f80dff9da0 [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user
get_irqnr_preamble allows machines to take some action before entering the
get_irqnr_and_base loop.  On iop we enable cp6 access.

arch_ret_to_user is added to the userspace return path to allow individual
architectures to take actions, like disabling coprocessor access, before
the final return to userspace.

Per Nicolas Pitre's note, there is no need to cp_wait on the return to user
as the latency to return is sufficient.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 15:04:29 +00:00
Russell King
ae0a846e41 [ARM] Move processor_modes[] to .../process.c
bad_mode() currently prints the mode which caused the exception, and
then causes an oops dump to be printed which again displays this
information (since the CPSR in the struct pt_regs is correct.)  This
leads to processor_modes[] being shared between traps.c and process.c
with a local declaration of it.

We can clean this up by moving processor_modes[] to process.c and
removing the duplication, resulting in processor_modes[] becoming
static.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-06 16:46:48 +00:00
Russell King
db6ccbb61c [ARM] Fix kernel-mode undefined instruction aborts
If the kernel attempts to execute a CP1 or CP2 instruction and it
aborts, and a FP emulator is not loaded, we try to return as if to
a user context, instead of the proper kernel context.  Since the
fault came from kernel mode, we must use the kernel return paths.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-06 22:53:48 +00:00
Lennert Buytenhek
afe4b25e7d [ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 17:52:22 +00:00
Russell King
7ad1bcb25c [ARM] Add ARM irqtrace support
This adds support for irqtrace for lockdep on ARM.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Nicolas Pitre
ba9b5d7637 [ARM] 3746/2: Userspace helpers must be Thumb mode interworkable
Patch from Nicolas Pitre

The userspace helpers in clean/arch/arm/kernel/entry-armv.S are called
directly in/from userspace. They need to cope with being called from
Thumb code.

Patch below uses the bx interworking instruction when
CONFIG_ARM_THUMB=y.

Based on an earlier patch from Paul Brook <paul@codesourcery.com>

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-18 17:20:15 +01:00
Linus Torvalds
a8c4c20dfa Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
2006-07-02 15:04:12 -07:00
Lennert Buytenhek
ae95bfbb2b [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
Patch from Lennert Buytenhek

This patch makes the iWMMXt context switch hook use the generic
thread notifier infrastructure that was recently merged in commit
d6551e884c.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 19:56:48 +01:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Lennert Buytenhek
c17fad11f3 [ARM] 3370/2: ep93xx: add crunch support
Patch from Lennert Buytenhek

Add the necessary kernel bits for crunch task switching.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:55:01 +01:00
Russell King
d6551e884c [ARM] Add thread_notify infrastructure
Some machine classes need to allow VFP support to be built into the
kernel, but still allow the kernel to run even though VFP isn't
present.  Unfortunately, the kernel hard-codes VFP instructions
into the thread switch, which prevents this being run-time selectable.

Solve this by introducing a notifier which things such as VFP can
hook into to be informed of events which affect the VFP subsystem
(eg, creation and destruction of threads, switches between threads.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-22 10:24:18 +01:00
Paul Brook
6896eec029 [ARM] 3420/1: Missing clobber in example code
Patch from Paul Brook

The example code in the source documentation for __kernel_dmb
clobbers r0 but doesn't list it the asm clobber list.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 22:19:29 +01:00
Russell King
5d25ac038a [ARM] Move IRQ enable after coprocessor number decode
Allow the individual coprocessor handlers to decide when to enable
interrupts, rather than unconditionally enabling them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:05:50 +00:00