The sw reset should be called prioir to enabling sw defined function,
according to datasheet.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Remove unnecessary headers from the file.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This patch adds analog and pll control setting. This control setting
is used for DP TX PHY block to set the values as below. It is beneficial
to improve analog characteristics.
- TX terminal registor is 50 Ohm.
- Reference clock of PHY is 24 MHz.
- Power source for TX digital logic is 1.0625 V.
- Power source for internal clock driver is 1.0625 V.
- PLL VCO range setting is 600 uA.
- Power down ring osc is turned off.
- AUX terminal resistor is 50 Ohm.
- AUX channel current is 8 mA and multiplied by 2.
- TX channel output amplitude is 400 mV.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
DP PLL Lock status should be checked in order to prevent unlocked PLL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Samsung EXYNOS SoC such Exynos5 has DP controller and embedded DP
panel can be used. This patch supports DP driver based on Samsung
EXYNOS SoC chip.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Jingoo Han