Commit graph

5 commits

Author SHA1 Message Date
Eric Miao
2029e5643a [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded IRQs
The irq_chip is not yet registered, so no default irq_chip.mask_ack(),
which we have to handle it correctly manually here.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-03-02 07:40:57 +08:00
Haojian Zhuang
df0c382436 [ARM] mmp2: add handling on PMIC IRQ
Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs
to be cleared after PMIC IRQ occured. Now append the clear operation in
irq chip handler.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-03-02 07:40:57 +08:00
Haojian Zhuang
16144bfb83 [ARM] mmp2: add gpio initialization
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-03-02 07:40:56 +08:00
Haojian Zhuang
4e3b4da98e [ARM] mmp2: add mask function in irq-mmp2.c
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-03-02 07:40:56 +08:00
Haojian Zhuang
2f7e8faef5 [ARM] mmp: add support for Marvell MMP2
Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's
ARMv6 compatible.  Support basic interrupt handler and timer,
and basic support for MMP2 based FLINT platform.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-03-02 07:40:55 +08:00