Failures during the dmm probe can cause the kernel to crash. Moved
the spinlock to a global and moved list initializations immediately
after the allocation of the dmm private structure.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Reviewed-by: Rob Clark <rob.clark@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch splits the DMM off into a separate sub-device, in order to
utilize the platform device information that was created as part of
the OMAP hwmod entry for the DMM.
The driver probe function queries the iomem resource and IRQ using
standard platform_get functions.
The OMAP DRM driver now calls the platform_driver_register() function
for the subordinate DMM driver inside its probe function. This
guarantees the required order for the DMM and ensures the DMM resources
are available for use by the DRM driver.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Added check for valid device information before dumping debugfs
information.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Right now just a tiler_map file to dump a 2d map of which areas in
tiler/dmm have pinned buffers (or reservations). In the future more
could be added.
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Add support for YWRAP scrolling by shuffling pages around in DMM
instead of sw blits.
Note that fbcon only utilizes this mode if the y resolution is
divided evenly by the font height. So, for example, a 1920x1080
display using a 16 pixel tall font will not utilize this, but a
1280x1024 display would.
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Dynamic Memory Manager (DMM) is a hardware block in the OMAP4+
processor that contains at least one TILER instance. TILER, or
Tiling and Isometric Lightweight Engine for Rotation, provides
IOMMU capabilities through the use of a physical address translation
table. The TILER also provides zero cost rotation and mirroring.
The TILER provides both 1D and 2D access by providing different views
or address ranges that can be used to access the physical memory that
has been mapped in through the PAT. Access to the 1D view results in
linear access to the underlying memory. Access to the 2D views result
in tiled access to the underlying memory resulted in increased
efficiency.
The TILER address space is managed by a tiler container manager (TCM)
and allocates the address space through the use of the Simple Tiler
Allocation algorithm (SiTA). The purpose of the algorithm is to keep
fragmentation of the address space as low as possible.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Andy Gross