Remove the individual 'struct clksrc_clks' and place them into an array
so that we can simply use s3c_register_clksrcs to register tham all in one
go.
Since the spdif clock relies on the audio clock, move the audio clocks
into their own arrary.
Thanks to Marek Szyprowski for testing and pointing out the four clocks
what where missed from the clock list.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Move the clock definitions around ready to turn the clocks into an array
of clocks and register them in one go.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Remove the copy of the old s3c64xx struct clksrc_clk and use the new one
in plat-samsung. This eliminates a bug in the set_parent() call where it
failed to set the clk->parent after sucesfully updating the clock.
The script that was used to automate much of the process will be supplied
seperately.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Reduce the size of struct clk by 12 bytes and make defining clocks with
common implementation functions easier by moving the set_rate, get_rate,
round_rate and set_parent calls into a new structure called 'struct clk_ops'
and using that instead.
This change does make a few clocks larger as they need their own clk_ops,
but this is outweighed by the number of clocks with either no ops or having
a common set of ops.
Update all the users of this.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Clocks hierarchy has been completely reimplemented to match the S5PC100
specification.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
S5PC100 and S5PC110 clock registers differs in many places, rename all
previously defined registers to be S5PC100 specific. Remove all power
management registers. They will be added later to a separate file.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
S5PC100 has 4 PLLs (APLL,MPLL,EPLL,HPLL) and 3 clock domains. Clock scheme is
implemented here.
Signed-off-by: Byungho Min <bhmin@samsung.com>
[ben-linux@fluff.org: edited title]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
