The msm provides timer hardware that is private to each core. Each
timer has separate counter and match registers, so we create separate
clock_event_devices for each core. For the global clocksource, use
cpu 0's counter.
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits)
ARM: DMA: add support for DMA debugging
ARM: PL011: add DMA burst threshold support for ST variants
ARM: PL011: Add support for transmit DMA
ARM: PL011: Ensure IRQs are disabled in UART interrupt handler
ARM: PL011: Separate hardware FIFO size from TTY FIFO size
ARM: PL011: Allow better handling of vendor data
ARM: PL011: Ensure error flags are clear at startup
ARM: PL011: include revision number in boot-time port printk
ARM: vexpress: add sched_clock() for Versatile Express
ARM i.MX53: Make MX53 EVK bootable
ARM i.MX53: Some bug fix about MX53 MSL code
ARM: 6607/1: sa1100: Update platform device registration
ARM: 6606/1: sa1100: Fix platform device registration
ARM i.MX51: rename IPU irqs
ARM i.MX51: Add ipu clock support
ARM: imx/mx27_3ds: Add PMIC support
ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()
mx51: fix usb clock support
MX51: Add support for usb host 2
arch/arm/plat-mxc/ehci.c: fix errors/typos
...
Conflicts:
MAINTAINERS
arch/arm/mach-omap2/pm24xx.c
drivers/scsi/bfa/bfa_fcpim.c
Needed to update to apply fixes for which the old branch was too
outdated.
Add USB OTG, peripheral and host devices. This patch also adds
usb_phy_clk which is required for resetting the PHY. VBUS power up
and shutdown routines depends on PMIC module. As PMIC driver is
unavailable, configure USB in peripheral only mode.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI. Recover the SGI number via do_IPI.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
On msm8x60, the MID field on the AXI connection to the
IOMMU can be up to five bits wide. Thus, allow the IOMMU
context platform data to map up to 32 MIDs.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Commit 7c63984b86 (ARM: do not define VMALLOC_END relative to PAGE_OFFSET)
changed VMALLOC_END to be an explicit value. Before this, it was
relative to PAGE_OFFSET and therefore converted to unsigned long
as PAGE_OFFSET is an unsigned long. This introduced the following
build warning. Fix this by changing the explicit defines of
VMALLOC_END to be unsigned long.
CC arch/arm/mm/init.o
arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int'
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Acked-by: Uwe Kleine-K <u.kleine-koenig@pengutronix.dee>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Define VMALLOC_END as an unsigned long to match expected type.
Eliminates a warning:
arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:606: warning: format '%08lx' expects type
'long unsigned int', but argument 12 has type 'unsigned int'
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
If the board has a debug uart the user is given a choice of which
uart to use. The user can also select NONE, which means not to use one.
In most of our header files when NONE is selected nothing is defined
for MSM_DEBUG_UART_PHYS or MSM_DEBUG_UART_BASE. This causes a compile
failure in debug-macro.S which expect something to be defined there.
Example of the failure,
arch/arm/kernel/built-in.o: In function `hexbuf':
linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_PHYS'
linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_BASE'
This fixes the compile failure by adding an ifdef to debug-macro.S
that removes all the debug uart code in the case of NONE.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Originally there was an ifdef case to handle when no debug uart
was selected. In commit 0ea1293009
that case was removed which causes the following build failure,
linux-2.6/arch/arm/kernel/debug.S: Assembler messages:
linux-2.6/arch/arm/kernel/debug.S:174: Error: bad instruction `addruart r1,r2'
linux-2.6/arch/arm/kernel/debug.S:176: Error: bad instruction `waituart r2,r3'
linux-2.6/arch/arm/kernel/debug.S:177: Error: bad instruction `senduart r1,r3'
linux-2.6/arch/arm/kernel/debug.S:178: Error: bad instruction `busyuart r2,r3'
linux-2.6/arch/arm/kernel/debug.S:190: Error: bad instruction `addruart r1,r2'
This is a partial revert to add back the case which was removed with
two caveats. First the API for the addruart macro was updated, and
the new addruart case now return 0xfff00000 so that a know IO mapping
is created instead of a random one.
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jason Wang <jason77.wang@gmail.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.
This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.
Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.
Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Add the platform data for the IOMMUs found on the Qualcomm
msm8x60 SoC.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Add support for the IOMMUs found on the upcoming Qualcomm
MSM8x60 chips. These IOMMUs allow virtualization of the
address space used by most of the multimedia cores on these
chips.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
The MSM8x60 has a different physical memory offset than other targets.
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Some MSM targets don't select the debug UART in this way. For those we
need to disable this selection mechanism.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
The existing MSM irq entry macro is specific to a VIC
implementation. Renaming this makes room for irq support based on
other interrupt controllers.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Board configuration for MSM8X60 emulation on RUMI3.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Define the interrupt map in irq-8x60.h
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
IRQ assignments are different for MSM8X60 than other existing MSMs.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
MSM8X60 has different IO mappings than previous MSMs.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Now that all supported gpio_tlmm_config-using boards
are using gpiomux, remove the deprecated code.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Add the 'gpiomux' api, which addresses the following shortcomings
of existing tlmm api:
- gpio power-collapse, which is managed by a peripheral processor on
other targets, must be managed by the application processor on the 8x60.
- The enable/disable flag of the legacy gpio_tlmm_config api
is not applicable on the 8x60, and causes confusion.
- The gpio 'direction' bits are meaningless for all func_sel
configurations except for generic-gpio mode (func_sel 0), in which
case the gpio_direction_* functions should be used. Having these
bits in the tlmm api leads to confusion and misuse of the gpiolib
api, and they have been removed in gpiomux.
- The functional api of the legacy system ran contrary to the typical
use-case, which is a single massive configuration at boot. Rather
than forcing hundreds of 'config' function calls, the new api
allows data to be configured with a single table.
gpiomux_get and gpiomux_put are meant to be called automatically
when gpio_request and gpio_free are called, giving automatic
gpiomux/tlmm control to those drivers/lines with simple
power profiles - in the simplest cases, an entry in the gpiomux table
and the correct usage of gpiolib is all that is required to get proper
gpio power control.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
VMALLOC_END is supposed to be an absolute value, while PAGE_OFFSET may
vary depending on the selected user:kernel memory split mode through
CONFIG_VMSPLIT_*. In fact, the goal of moving PAGE_OFFSET down is to
accommodate more directly addressed RAM by the kernel below the vmalloc
area, and having VMALLOC_END move along PAGE_OFFSET is rather against
the very reason why PAGE_OFFSET can be moved in the first place.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Rename mmc_platform_data to msm_mmc_platform_data as it is used
only by MSM platform.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Add msm_add_sdcc() prototype to mach/board.h to fix the
checkpatch warning.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
[dwalker@codeaurora.org: renamed to trout, checkpatch cleanup]
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* 'msm-mmc_sdcc' of git://codeaurora.org/quic/kernel/dwalker/linux-msm:
drivers: mmc: msm_sdcc: Add EMBEDDED_SDIO support
mmc: msm_sdcc: Fix issue where clocks could be disabled mid transaction
mmc: msm_sdcc: Fix the dma exec function to use the proper delays
mmc: msm_sdcc: Don't set host->curr.mrq until after we're sure the busclk timer won't fire
mmc: msm_sdcc: Enable busclk idle timer for power savings
mmc: msm_sdcc: Don't disable interrupts while suspending
mmc: msm_sdcc: Fix issue where we might not end a sucessfull request
mmc: msm_sdcc: Featurize busclock power save and disable it by default
mmc: msm_sdcc: Fix bug where busclk expiry timer was not properly disabled
mmc: msm_sdcc: Reduce command timeouts and improve reliability.
mmc: msm_sdcc: Schedule clock disable after probe
mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays
mmc: msm_sdcc: Driver clocking/irq improvements
msm: Add 'execute' datamover callback
mmc: msm_sdcc: Snoop SDIO_CCCR_ABORT register
mmc: msm_sdcc: Clean up clock management and add a 10us delay after enabling clocks
The MSM7x30 does not have a separate bank of memory for shared
memory communication with the radio CPU. Set the kernel base
address 2MB in, to use this first 2MB for this purpose.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The MSM SOC's DMA controller contains several security domains.
On the MSM7x00, only security domain 3 is accessible to our CPU.
The 7x30, however, uses security domain 2. Fix up the register
definition macros to select this appropriately, based on
configured target.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Add a header describing the io regions for MSM7x30.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Support different RAM base addresses used by Qualcomm SOCs, with
QSD8x50 as the first addtional one.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Add a header describing the io regions for QSD8x50.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
GPIO support for Qualcomm SOCs requires interaction with the
radio (baseband processor). This API allows the different boards
to enable GPIO through the radio processor in a generic way.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The 'PCOM' method of clock control (commands issued to the radio
CPU) is shared across several (but not all) Qualcomm SOCs.
Generalize this clock mechanism so these other SOCs can be added.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Scorpion-based SOCs from Qualcomm use a different interrupt
controller 'sirc'.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm_iomap.h is specific to the MSM7x00 series devices. Generalize
this in preparation to support more devices.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
irqs.h is specific to the MSM7x00 series devices. Generalize
this in preparation to support more devices.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
