Add GPIO configuration and platform specific declarations
to make Mitac Mio A701 camera chip work. The chip is a
Micron MT9M111 CMOS sensor, based on PXA QIF interface and
I2C bus for sensor control.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Since mioa701 board has migrated to the mfp architecture,
low power gpio setup is now correctly handled even when gpio
led driver is not loaded, and leds and vibrator don't stay
activated in suspend mode (especially vibrator).
Remove the not needed anymore dependency.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Add IO memory and IRQ ressources for pxa based SoC to be
able to use the new rtc-pxa driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
This patch implements Eric Miao's idea to detect the correct value of
sdram_rows by inspecting the MDCNFG register settings.
It is only tested on two pxa27x devices with 64MB RAM (magician and
hx4700) so far.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Following the removal of the "->policy" usage for PXA255 in patch
459fc208ab (cpufreq: remove
policy->governor setting in drivers initialization), this patch
introduces an option (called "pxa255_turbo_table") to select either
the "run" or "turbo" frequency table.
It also cures the runtime warning that was printed each time the
frequency was changed.
Got rid of all references to CPUFREQ_POLICY_* for pxa255, and sticked
with the run/turbo thing.
Tested on an Arcom/Eurotech Viper.
Signed-off-by: Marc Zyngier <maz@misterjones.org>
Acked-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
This symbol is required by locomo backlight driver, exporting this
allows the driver to be built as a module.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
GPIO3/GPIO4 are a bit special on pxa27x, since it depends on PCFR/PI2C_EN
bit, add their definitions here with comments.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Acked-by: Stefan Schmidt <stefan@datenfreihafen.org>
PXA935 has changed its implementor ID from Intel to Marvell, this
patch modifies arch/arm/boot/compressed/head.S and proc-xsc3.S to
support a smooth bootup.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Let's put these devices into a central place even if they are now
processor specific, as they might be re-used in later processors.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
The optimal change would be to move the AC97 register definitions into
the AC97 driver, unfortunately, the registers are shared between several
files. Move them into a dedicated regs-ac97.h first.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
There two are internal registers that are used to control the power
management of the Internal Memory (i.e. Internal SRAM). They are
referenced nowhere and removed here to simplify pxa-regs.h a bit.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
We now have generic PWM API for PXA, the PWM registers definitions are
now used nowhere, and it is not encouraged to manipulate them directly
by driver code.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
pxa_gpio_{get,set}_value() are not used anymore, remove them from hardware.h.
Declaration of pxa_gpio_mode() is still being referenced and thus moved into
pxa2xx-gpio.h
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Original patch from Marek Vasut, the problems with PXA26x are:
1. there are additional 4 GPIOs 86,87,88,89 have their direction bits
inverted in GPDR2, as well as their alternate function bits being
'1' for their GPIO functionality in GAFRx
2. there is no easy way to decide if the processor is a pxa26x or a
pxa250/pxa255 at run-time, so the assumption here is the pxa26x
will be treated as one of the pxa25x variants, and board code
should have a better knowledge of the processor it is featured
Introduce pxa26x_init_irq() for the second purpose, and treat the
additional GPIOs > 85 on PXA25x specially.
Kconfig option CONFIG_CPU_PXA26x is introduced to optimize the code
a bit when PXA26x support isn't needed. Board config options have
to select this to enable the support for PXA26x.
__gpio_is_inverted() will be optimized way when CONFIG_CPU_PXA26x
isn't selected.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
This reverts commit da1a3dc0eb.
The originally proposed way in the above commit is incorrect. And
there is no easy way to distinguish between pxa25x and pxa26x at
run-time.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
The 'gpio_nr' can really be inferred by 'pxa_last_gpio', and since we
already have that variable, remove the unnecessary 'gpio_nr' now.
Also, fix the incorrect GPIO number passed in pxa27x_init_irq().
Note: pxa_last_gpio should be initialized earlier, and this is true
since it's been assigned in machine_desc->init_irq().
Signed-off-by: Eric Miao <eric.miao@marvell.com>
PXA SoC have several GPIOs muxed on only one wakeup source.
Add support for these wakeup sources which were missing
in mfp core support.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
This patch makes do_hw_reset the default reboot behavior when nothing
else matches. This restores reboot functionality on gumstix basix
devices where reboot=cold is the default boot argument.
Signed-off-by: Jaya Kumar <jayakumar.lkml@gmail.com>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The original incorrect configuration caused GPIO79_nCS_3 being overriden,
thus resulted in the NAND flash not being detected. The real PSKTSEL pin
is on GPIO104 instead of GPIO79.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
FLASH_* and EPROM_* constants are unused, and clash with drivers:
drivers/atm/ambassador.h:257:1: warning: "FLASH_BASE" redefined
drivers/atm/ambassador.h:258:1: warning: "FLASH_SIZE" redefined
drivers/atm/iphase.h:332:1: warning: "EPROM_SIZE" redefined
so remove them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/dma-mapping.c: In function `dma_sync_sg_for_cpu':
arch/arm/mm/dma-mapping.c:588: warning: statement with no effect
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that the critical read back to flush the next descriptor address is
fixed we can downgrade some BUG_ONs that need only be enabled when testing
changes to the driver.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Mikael Pettersson reported:
The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0
(the first ethernet port) on my Thecus n2100 XScale box.
There is however still a strange "ghost" device that gets partially
detected in 2.6.28-rc2 vanilla.
The IOP321 manual says:
The user designates the memory region containing the OCCDR as
non-cacheable and non-bufferable from the IntelR XScaleTM core.
This guarantees that all load/stores to the OCCDR are only of
DWORD quantities.
Ensure that the OCCDR is so mapped.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Same fix as commit c7cf72dcad: when 'start' and 'end' are less than a
cacheline apart and 'start' is unaligned we are done after cleaning and
invalidating the first cacheline.
Cc: <stable@kernel.org>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When 'start' and 'end' are less than a cacheline apart and 'start' is
unaligned we are done after cleaning and invalidating the first
cacheline. So check for (start < end) which will not walk off into
invalid address ranges when (start > end).
This issue was caught by drivers/dma/dmatest.
2.6.27 is susceptible.
Cc: <stable@kernel.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Cc: Lennert Buytenhek <buytenh@marvell.com>
Cc: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
As of 73bdf0a60e, the kernel needs
to know where modules are located in the virtual address space.
On ARM, we located this region between MODULE_START and MODULE_END.
Unfortunately, everyone else calls it MODULES_VADDR and MODULES_END.
Update ARM to use the same naming, so is_vmalloc_or_module_addr()
can work properly. Also update the comment on mm/vmalloc.c to
reflect that ARM also places modules in a separate region from the
vmalloc space.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
