This patch adds support Power Domain for S5PV310 and S5PC210.
Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch is applied according to the commit 1a8e41cd67
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).
Actually, S5PV310 has same cache controller(PL310).
Following is from Catalin Marinas' commit.
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds DMC io mapping for access it and adds registers.
This is used in checking DRAM memory type.
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support SROMC for S5PV310 and S5PC210.
Signed-off-by: Daein Moon <moon9124@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310.
It includes TAG and Data latency, Prefetch, and Power configurations.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds initial map for GPIO2 and GPIO3.
S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds initialization HSMMC device information.
And HSMMC platform data like card detect, data bus width
and capability is configured.
Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch fixes build error about GPIO address due to
conflict of commit 4d914705 and 19a2c065.
- commit 4d914705: Fix on GPIO base addresses
- commit 19a2c065: Moves initial map for merging S5P64X0
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch moves some initial maps from plat-s5p to machine,
so that can merge mach-s5p6440 and mach-s5p6450.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Following occurs on boot message without this patch.
CPU1: processor failed to boot
Brought up 1 CPUs
SMP: Total of 1 processors activated...
This patch adds SYSRAM mapping for fixing Secondary CPU startup.
CPU1: Booted secondary processor
Brought up 2 CPUs
SMP: Total of 2 processors activated...
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds CMU block for S5PV310/S5PC210 clock.
(CMU: Clock Management Unit)
Of course, changed current clock addresses for it together.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds Samsung S5PV310/S5PC210 CPU support.
The S5PV310/S5PC210 integrates a ARM Cortex A9 multi-core.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Jiseong Oh <jiseong.oh@samsung.com>
[kgene.kim@samsung.com: fix build errors]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
