Commit graph

4 commits

Author SHA1 Message Date
Nicolas Pitre
f91a8dcc25 [ARM] cache align memset and memzero
This is a natural extension following the previous patch.
Non Feroceon based targets are unchanged.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:44:39 +02:00
Russell King
1b93a71755 [ARM] Remove LOADREGS macro
As for RETINSTR, LOADREGS is a left-over from the 26-bit days.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:23:45 +01:00
Russell King
7999d8d7a6 [ARM] Remove RETINSTR macro
RETINSTR is a left-over from the days when we had 26-bit and
32-bit CPU support integrated into the same tree.  Since this
is no longer the case, we can now remove RETINSTR.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:17:23 +01:00
Linus Torvalds
1da177e4c3 Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
2005-04-16 15:20:36 -07:00