Commit Graph

12 Commits (5febf1cd79425d3c65d9a66a2299f0d06dc4b1eb)

Author SHA1 Message Date
Paul Mundt cb7af21f7d sh: Use boot_cpu_data for CPU probe.
This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-27 18:18:39 +09:00
Magnus Damm 2eb0303c2c sh: intc - add support for sh7206
This patch converts the cpu specific interrupt setup code for sh7206
from ipr to intc. New vectors are also added to match the information
provided by the datasheet.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:50 +09:00
Magnus Damm c4773bc2a0 sh: fix irqs for the second serial port on sh7206
This patch makes sure the serial port interrupt irqs matches the
datasheet.  Only irqs for SCIF1 are changed. While at some cosmetic
spaces are added.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:50 +09:00
Magnus Damm 90015c8938 sh: IPR/INTC2 IRQ setup consolidation.
This patch unifies the cpu specific interrupt setup functions for
interrupt controller blocks such as ipr, intc2 and intc. There is no
point in having separate functions for each interrupt controller, so
let's clean this up.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-07-20 12:18:20 +09:00
Magnus Damm 68abdbbb03 sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together
with the ipr_data structure in a new data structure called ipr_desc.
This new structure also contains the name of the controller in struct
irq_chip. The idea behind putting struct irq_chip in there is that we
can use offsetof() to locate the base addresses in the irq_chip
callbacks. This strategy has much in common with the recently merged
intc2 code.

One logic change has been made - the original ipr code enabled the
interrupts by default but with this patch they are all disabled by
default.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-06-15 18:56:19 +09:00
Paul Mundt 074f98df05 sh: Add 32-bit opcode feature CPU flag.
Add a CPU flag for the CPUs that support 32-bit opcodes, which
gets passed down to userspace.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-05-09 01:35:01 +00:00
Paul Mundt bd0799977c sh: Support for SH-2A 32-bit opcodes.
SH-2A supports both 16 and 32-bit instructions, add a simple helper
for figuring out the instruction size in the places where there are
hardcoded 16-bit assumptions.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-05-09 01:35:01 +00:00
Tobias Klauser c5a69d57eb Storage class should be before const qualifier
The C99 specification states in section 6.11.5:

The placement of a storage-class specifier other than at the
beginning of the declaration specifiers in a declaration is an
obsolescent feature.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2007-02-17 20:11:19 +01:00
Paul Mundt 11c1965687 sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-02-13 10:54:45 +09:00
Yoshinori Sato 5c67cd05e3 sh: sh7619 / sh7206 IPR initialize update
IPR initialize proceduere update.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-02-13 10:54:43 +09:00
Yoshinori Sato 780a156888 sh: IPR IRQ updates for SH7619/SH7206.
This updates the SH7619 and SH7206 code for the IPR IRQ changes.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2006-12-12 08:42:07 +09:00
Yoshinori Sato 9d4436a6fb sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619
(SH-2) MMU-less CPUs.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2006-12-06 10:45:36 +09:00