Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch. This renames local_*_hw() to hard_local_*() using the
following perl command:
perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`
and then fixing up asm/irqflags.h manually.
Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.
Signed-off-by: David Howells <dhowells@redhat.com>
The RTC ISTAT bits do not affect wakeups, and the RTC driver already
takes care of clearing this MMR when necessary. So drop the useless
clearing in the core Blackfin power code.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The dma_memcpy() function takes care of flushing different caches for us.
Normally this is what we want, but when resuming from mem, we don't yet
have caches enabled. If these functions happen to be placed into L1 mem
(which is what we're trying to relocate), then things aren't going to
work. So define a non-cache dma_memcpy() variant to utilize in situations
like this.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Anomaly 05000491 says that IFLUSH cannot have certain types of memory
stalls triggered before it has completed in order to function correctly.
One such condition is that it be in L1 instruction. So add a config
option to move it there, default it to on, and throw up a warning when
it is turned off and this anomaly exists.
Since the anomaly should be worked around, we can drop the older method
of calling IFLUSH multiple times.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Design found that these anomalies had the same root issue, so they've
merged 475 into 220. We need to do the same to update to the latest
anomaly sheets.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tweak the for loops that operate on the SIC IAR system MMRs to avoid
re-reading them multiple times in a row. System MMRs are a little
slower to access, so avoid the penalty when possible.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch removes a custom GPIO wakeup API which allowed GPIOs to act
as wakeup sources, which are not configured as Interrupts.
This API is a leftover from the time before irq_wake was established.
From now on people must use enable_irq_wake(GPIO_IRQx) and the GPIO in
question needs to be configured as Interrupt.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
Need to make sure we update the loops_per_jiffy values when we start
changing the core clock.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The exact hardware error handling code was added before the workaround
for anomaly 283 which caused the anomaly to be triggered in some cases
(an infinite core stall). So re-order the code to avoid this.
Reported-by: Andrew Rook <andrew.rook@speakerbus.co.uk>
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The on-chip keypad peripheral requires different registers to be setup
depending on the standby type (standby vs hibernation). However, since
the power management framework doesn't differentiate between these types,
the driver doesn't know which registers to program and subsequently it
avoids doing so.
Always enabling the keyboard wakeup source causes misbehavior when the
pins are not assigned to the keypad. If they happen to drive a certain
level, they'll trigger a wake up event which is not wanted. So until
the aforementioned issue can be sorted out, drop support for the
wakeup source completely.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch provides infrastructure for MAC Wake-On-Lan and PHYINT use in
phylib. New Interrupts added:
IRQ_MAC_PHYINT /* PHY_INT Interrupt */
IRQ_MAC_MMCINT /* MMC Counter Interrupt */
IRQ_MAC_RXFSINT /* RX Frame-Status Interrupt */
IRQ_MAC_TXFSINT /* TX Frame-Status Interrupt */
IRQ_MAC_WAKEDET /* Wake-Up Interrupt */
IRQ_MAC_RXDMAERR /* RX DMA Direction Error Interrupt */
IRQ_MAC_TXDMAERR /* TX DMA Direction Error Interrupt */
IRQ_MAC_STMDONE /* Station Mgt. Transfer Done Interrupt */
On BF537/6 the implementation is not straight forward since there are now
two chained chained_handlers. A cleaner approach would have been to add
latter IRQs to the demux of IRQ_GENERIC_ERROR.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We want to report all system calls (even invalid ones) to the tracing
layers, so check the NR only after we've notified.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
On Blackfin systems, the hardware single step exception triggers before
the system call exception, so we need to save this info to process it
later on. Otherwise, single stepping in userspace misses a few insns
right after the system call.
This is based a bit on the SuperH code added in commit 4b505db9c4.
Reported-by: Roland McGrath <roland@redhat.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This functions are implicitly called by core functions like cpu_relax(),
and since those functions may be called early on before common code has
initialized the per-cpu data area, we need to tweak the stats gathering.
Now the statistics are maintained in common bss which makes these funcs
safe to use as soon as the C runtime env is setup.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This makes room for off-chip IRQ controllers.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
During very early init, the stack pointer is given a slightly incorrect
value (&init_thread_union). The value is later adjusted to the right one
during early init (&init_thread_union + THREAD_SIZE), but it is used a few
times in between. While the few functions used don't actually put things
onto the stack (due to optimization), it's best if we simply use the right
value from the start.
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
SMP systems require per-cpu local clock event devices in order to enable
HRT support. One a BF561, we can use local core timer for this purpose.
Originally, there was one global core-timer clock event device set up for
core A.
To accomplish this feat, we need to split the gptimer0/core timer logic
so that each is a standalone clock event. There is no requirement that
we only have one clock event source anyways. Once we have this, we just
define per-cpu clock event devices for each local core timer.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the Blackfin IRQ controller supports this, drivers get the normal
functionality of controlling which CPU to bind IRQs to.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Sometimes a SMP system will randomly panic at boot. This is due to caches
being out of sync when one core tries to signal the other. So when one
core calls another via IPI, flush the data caches.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The error masks are only needed in the BF537 demux error code, so instead
of needing all the short peripheral defines in global space, push these
masks into the one file where they are actually needed. This fixes a
bunch of define collisions with common code (can/serial/etc...).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Barry Song <barry.song@analog.com>
When testing PREEMPT_RT kernel on BF561-EZKit, the kernel blocks while
booting. When the kernel initializes the ethernet driver, it sleeps and
never wakes up.
The issue happens when the kernel waits for a timer for Core B to timeout
(the timers are per-cpu based: static DEFINE_PER_CPU(struct tvec_base *,
tvec_bases) = &boot_tvec_bases).
However, the ksoftirqd thread for Core B (note, the ksoftirqd thread is
also per-cpu based) cannot work properly, and the timers for Core B never
times out.
When ksoftirqd() for the first time runs on core B, it is possible core A
is still initializing core B (see smp_init() -> cpu_up() -> __cpu_up()).
So the "cpu_is_offline()" check may return true and ksoftirqd moves to
"wait_to_die".
So delay the core b start up until the per-cpu timers have been set up
fully.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The GPIOs on ports C/D/E on the BF538/BF539 do not behave the same way as
the other ports on the part and the same way as all other Blackfin parts.
The MMRs are programmed slightly different and they cannot be used to
generate interrupts or wakeup a sleeping system. Since these guys don't
fit into the existing code, create a simple gpiolib driver for them.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
PLL_LOCKCNT applies only to the PLL programming sequence which does not
apply to core and system clock dividers. Writes to PLL_DIV to change the
CSEL/SSEL dividers take effect immediately.
There is still overhead in software in writing the new dividers, so just
use a value of 50us as this should be good enough.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
New helper - sys_mmap_pgoff(); switch syscalls to using it.
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
To set zeroes the sizeof the struct should be used rather
than sizeof the pointer, kzalloc does that.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Parts that have on-chip L2 SRAM cannot safely utilize writeback caching
mode, so reject any attempts to use it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the return from alloc_percpu is compatible with the address
of per-cpu vars, it makes sense to hand around the address of per-cpu
variables. To make this sane, we remove the per_cpu__ prefix we used
created to stop people accidentally using these vars directly.
Now we have sparse, we can use that (next patch).
tj: * Updated to convert stuff which were missed by or added after the
original patch.
* Kill per_cpu_var() macro.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Tejun Heo <tj@kernel.org>
Reviewed-by: Christoph Lameter <cl@linux-foundation.org>
Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.
It also removes:
- verbose GPL text(refer to the top level ./COPYING file)
- file names (you are looking at the file)
- bug url (it's in the ./MAINTAINERS file)
- "or later" on GPL-2, when we did not have that right
It also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The CPLB implementations (mpu/nompu) had exact copies of the cacheinit
code. Even the i/d cache functions are largely the same. So unify them
both in the common kernel cache code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make sure our interrupt entry code with exact hardware errors handles
anomaly 05000283 (infinite stall in system MMR kill) so we don't stall
while under load.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The majority of the time we are returning to user space, it is not in the
fixed atomic code region. So rather than branch to a function where we
check the PC and return, do the check inline and branch only when needed.
Also, tweak some of the fixed code handling based on assumptions we are
aware of but cannot be expressed in C.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
No one uses these functions, and some are duplicate of existing C code. So
just punt the whole thing.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper
sync procedures as laid out in the Blackfin programming manual. So rather
than audit/fix every call location, create helper functions that do the
right things in order to safely update these MMRs. Then convert all call
sites to use these new helper functions.
While we're fixing the code, drop the workaround for anomaly 05000125 as
that anomaly applies to old versions of silicon that we do not support.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Since the hardware only provides reporting for the last exception handled,
and the values are valid only when executing the exception handler, we
need to save the context for reporting at a later point. While we do this
for one exception, it doesn't work properly when handling a second one as
the original exception is clobbered by the double fault. So when double
fault debugging is enabled, create a dedicated shadow of these values and
save/restore out of there. Now the crash report properly displays the
first exception as well as the second one.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Allow hardware errors to be caught during early portions of booting, and
leave something in the shadow console that people can use to debug their
system with (to be printed out by the bootloader on next reset).
This enables the hardare error interrupts in head.S, allowing us to find
hardware errors when they happen (well, as much as you can with a hardware
error) and prints out the trace if it is enabled. This will catch errors
(like booting the wrong image on a 533) which previously resulted in a
infinite loop/hang, as well as random hardware errors before before
setup_arch().
To disable this debug only feature - turn off EARLY_PRINTK.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Cleanup is performed in two ways:
- remove extraneous updates of IPEND[4] w/ CONFIG_IPIPE,
and document remaining use.
- substitute pop-reg-from-stack instructions with plain SP fixups in
all save-RETI-then-discard patterns.
Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The purpose of the EVT14 handler may depend on whether CONFIG_IPIPE is
enabled, albeit its implementation can be the same in both cases. When
the interrupt pipeline is enabled, EVT14 can be used to raise the core
priority level for the running code; when CONFIG_IPIPE is off, EVT14
can be used to lower this level before running softirq handlers.
Rename evt14_softirq to evt_evt14 to pick an identifier that fits
both, which allows to reuse the same vector setup code as well.
Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We handle many exceptions at EVT5 (hardware error level) so that we can
catch exceptions in our exception handling code. Today - if the global
interrupt enable bit (IPEND[4]) is set (interrupts disabled) our trap
handling code goes into a infinite loop, since we need interrupts to be
on to defer things to EVT5.
Normal kernel code should not trigger this for any reason as IPEND[4] gets
cleared early (when doing an interrupt context save) and the kernel stack
there should be sane (or something much worse is happening in the system).
But there have been a few times where this has happened, so this change
makes sure we dump a proper crash message even when things have gone south.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Check that the result of kmalloc is not NULL before passing it to other
functions.
In the first two cases, the new code returns -ENOMEM, which seems
compatible with what is done for similar functions for other architectures.
In the last two cases, the new code fails silently, ie just returns,
because the function has void return type.
The semantic match that finds this problem is as follows:
(http://www.emn.fr/x-info/coccinelle/)
// <smpl>
@@
expression *x;
identifier f;
constant char *C;
@@
x = \(kmalloc\|kcalloc\|kzalloc\)(...);
... when != x == NULL
when != x != NULL
when != (x || ...)
(
kfree(x)
|
f(...,C,...,x,...)
|
*f(...,x,...)
|
*x->f
)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
On Blackfin SMP, a per-cpu loops_per_jiffy is pointless since both cores
always run at the same CCLK. In addition, the current implementation has
flaws since the main consumer for loops_per_jiffy (asm/delay.h) uses the
global kernel loops_per_jiffy and not the per_cpu one. So punt all of the
per-cpu handling and go back to the global shared one.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Improve the assembly with a few explanatory comments and use symbolic
defines rather than numeric values for bit positions.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache. Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem. The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.
So split the configure options such that they properly reflect the settings
that are applied to the hardware.
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The irq_panic function is only used when CONFIG_DEBUG_ICACHE_CHECK is
enabled, so move the conditional build to the Makefile rather than
wrapping all of the contents of the file.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Convert to test_bit() as that is what pretty much everyone uses and allows
us to migrate asm/bitops.h to the asm-generic version.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When a low priority interrupt (like ethernet) is triggered between 2 high
priority IPI messages, a deadlock in disable_irq() is hit by the second
IPI handler. This is because the second IPI message is queued within the
first IPI handler, but the handler doesn't process all messages, and new
ones are inserted rather than appended. So now we process all the pending
messages, and append new ones to the pending list.
URL: http://blackfin.uclinux.org/gf/tracker/5226
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The KGDB code uses this when switching processors to make sure the icache
is in a valid state.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We don't need to handle CPLB protection violations unless we are running
with the MPU on. Fix the entry code to call common trap_c, and remove the
code which is never run. This allows the traps test suite to run on older
boards with the MPU disabled.
URL: http://blackfin.uclinux.org/gf/tracker/5129
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Rather than having to maintain a hard coded list of Blackfin variants, use
the SIC defines themselves. This fixes build problems on BF51x/BF538 under
some configurations as they were missing from one of the lists.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Commit 6b3087c6 (which introduced Blackfin SMP) broke command line passing
when the DEBUG_DOUBLEFAULT config option was enabled. Switch the code to
using a scratch register and not R7 which holds the command line.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Per-processor Data Area isn't actually reserved by this function, and
all it ended up doing was issuing a printk(), so punt it.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Hardware errors on the Blackfin architecture are queued by nature of the
hardware design. Things that could generate a hardware level queue up at
the system interface and might not process until much later, at which
point the system would send a notification back to the core.
As such, it is possible for user space code to do something that would
trigger a hardware error, but have it delay long enough for the process
context to switch. So when the hardware error does signal, we mistakenly
evaluate it as a different process or as kernel context and panic (erp!).
This makes it pretty difficult to find the offending context. But wait,
there is good news somewhere.
By forcing a SSYNC in the interrupt entry, we force all pending queues at
the system level to be processed and all hardware errors to be signaled.
Then we check the current interrupt state to see if the hardware error is
now signaled. If so, we re-queue the current interrupt and return thus
allowing the higher priority hardware error interrupt to process properly.
Since we haven't done any other context processing yet, the right context
will be selected and killed. There is still the possibility that the
exact offending instruction will be unknown, but at least we'll have a
much better idea of where to look.
The downside of course is that this causes system-wide syncs at every
interrupt point which results in significant performance degradation.
Since this situation should not occur in any properly configured system
(as hardware errors are triggered by things like bad pointers), make it a
debug configuration option and disable it by default.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When possible, work around anomaly 05000220 (external memory is write
back cached, but L2 is not cached). If not possible, detect the
conditions at build time and reject any qualifying configurations.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
For systems where the core cycles are not a usable tick source (like SMP
or cycles gets updated), enable gptimer0 as an alternative.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add some notes for anomaly 05000120 to make sure we work around it.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Detect and reject operating conditions for anomaly 05000274 since the
problem cannot be worked around in software.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Workaround anomaly 05000227 by only using the scratch pad for stack when
absolutely necessary. The core code which reprograms clocks really only
touches MMRs directly with constants.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Simplify the do_flush macro now that we don't need to take into account
a second instruction being used together.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
ipipe-2.6.28.9-blackfin-git95aafe6.patch
Singed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make sure we flush all data caches and their write buffers before flushing
icache, otherwise random edge cases could crop up where stale data is read
into icache from external memory. As fallout, punt the combined icache +
dcache flush function since we cannot safely do them back to back -- the
SSYNC is needed between the dcache flush and the icache flush.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Move exception stack mess from entry.S to init.c to fix link failure when
CONFIG_EXCEPTION_L1_SCRATCH is in use.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Random read/write errors are a bad thing - so don't let anyone
(including the test bench) run on something we know is bad.
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Run IFLUSH twice to avoid loading wrong instruction
after invalidating icache and following sequence is met.
1) The one instruction address is cached in the icache.
2) This instruction in SDRAM is changed.
3) IFLASH[P0] is executed only once in lackfin_icache_flush_range().
4) This instruction is executed again, but not the changed new one.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
IMHO the setting should depend on ANOMALY_05000305 which is about the
availability of the bit, not ANOMALY_05000265 which only describes the
SPORT sensitivity to noise (checked for BF561 only, though).
If that's not true for other BF variants, maybe the definition of
ANOMALY_05000265 for BF561 should be changed to '(1)' instead.
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Barry Song