This patch exports the VPU and VEU blocks of the sh7722 to user space
using the uio_pdrv_genirq platform driver.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch exports the VPU and VEU blocks of the sh7343 to user space
using the uio_pdrv_genirq platform driver.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch is
By sh2
- Remove duplicate code
- Reduce stack usage
- Cleanup and little optimize
By sh2a
- Add missing handler(256 to 511)
- Use sh2a instructions handler
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds platform data for the single I2C channel on sh7366.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds platform data for the single I2C channel on sh7723.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds platform data for two I2C channels to the sh7343.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch is based on interrupt acknowledge code for external
interrupt sources on sh3 processors and adds on sh4a processors.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch contains the following cleanups:
- make the following needlessly global code static:
- cf-enabler.c: cf_init()
- cpu/clock.c: __clk_enable()
- cpu/clock.c: __clk_disable()
- process_32.c: default_idle()
- time_32.c: struct clocksource_sh
- timers/timer-tmu.c: struct tmu_timer_ops
- remove the following unused functions (no CONFIG_BLK_DEV_FD on sh):
- process_{32,64}.c: disable_hlt()
- process_{32,64}.c: enable_hlt()
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7763 has 3 SCIF device. Current code supports SCIF0 and 1.
SCIF0 and 1 are same register constitution, but only SCIF2 is different.
I added support of SCIF2.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7763's setup code use old DECLARE_INTC_DESC.
There was a compile error because of this.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch fixes the following build error caused by
commit a1dc4b59fa
(sh: intc_sh5 depends on cayman board for IRQ priority table.):
<-- snip -->
...
CC arch/sh/kernel/cpu/irq/intc-sh5.o
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c: In function 'plat_irq_setup':
/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c:257: error: expected declaration or statement at end of input
make[4]: *** [arch/sh/kernel/cpu/irq/intc-sh5.o] Error 1
<-- snip -->
Reported-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This was copied over from the previous MobileR bits, which doesn't
apply to R2. The URAM block on R2 is recycled for the L2 instead.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for sh7723 silicon with a prr value of 0x51.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch fixes a VPU vector typo for sh7723. The correct value is 0x980,
the same as for sh7722.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The USBF function on sh7722 is currently not working with the m66592_udc
driver. The driver is using platform_get_resource_byname() so my commit
a0d29798e5 broke sh7722 support.
The long term fix is to replace platform_get_resource_byname() in the
driver with platform_get_resource(), but this helps until that happens.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
'ix' is unsigned but denormal_subf1() may return a negative int.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The processor models sh7706, sh7707 and sh7709 don't support high
level trigger sense configuration. And the intc code looks like
crap these days so what's the difference.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Clean up the intc tables by removing unneeded #ifdefs. The vector
list is what selects which interrupt sources that should be added,
having unsupported bitfields listed is ok as long as the vector
is excluded from the list.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds interrupt acknowledge code for external interrupt
sources on sh3 processors. Only really required for edge triggered
interrupts, but we ack regardless of sense configuration.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch unifies the sh3 external irq pin code. It buys us some
savings with reduced code redundancy, but the main feature with
this change is irq sense selection support for all sh3 processors.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The SH-4A series probe we were relying on doesn't work any more on the
newer parts, bump this up to use CVR.CHIP instead so we have consistent
behaviour across all of the parts, which is what this should have been
testing in the first place.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add platform data for the SuperH Mobile I2C block to sh7722.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Use physical addresses and change resource name to follow data sheet.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently with preempt enabled there's the possibility to be preempted
after the TIF_USEDFPU test and the register save, leading to bogus
state post-__switch_to(). Use an explicit preempt_disable()/enable()
pair around unlazy_fpu()/clear_fpu() to avoid this. Follows the x86
change.
Reported-by: Takuo Koguchi <takuo.koguchi.sw@hitachi.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently the SH-2/SH-2A address error exception dispatch copies off the
register state from the stack and skips over the first register, skewing
the rest. Fix up the math here so that the proper register state is
handed down to the exception handler itself.
Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
__FUNCTION__ is gcc-specific, use __func__
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This header is needed on other architectures as well (namely h8300),
which currently fails to build without this in place. Rather than
duplicating the port definition completely there, just move this to a
common location instead.
This should get h8300 working again for 2.6.25, in addition to the
changes already pushed by Sato-san in -rc2.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Fix the RTC resources setup for sh770x. Whit these proper
start values RTC driver (drivers/rtc/rtc-sh.c) works.
Signed-off-by: Rafael Ignacio Zurita <rizurita@yahoo.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The C99 specification states in section 6.11.5:
The placement of a storage-class specifier other than at the
beginning of the declaration specifiers in a declaration is an
obsolescent feature.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
drivers/char/pcmcia/synclink_cs.c:284:1: warning: "CCR3" redefined
In file included from include/asm/cache.h:13,
from include/asm/processor_32.h:15,
from include/asm/processor.h:60,
from include/linux/prefetch.h:14,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/char/pcmcia/synclink_cs.c:38:
include/asm/cpu/cache.h:38:1: warning: this is the location of the previous definition
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds sh7366 cpu supports. Just the most basic things like interrupt
controller, clocks and serial port are included at this point.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes the maskreg irq code since it is not in use anymore.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for sh7722 devices with prr value 0xa1.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Using "attr" twice is not OK, because it effectively prohibits such
container_of() on variables not named "attr".
Signed-off-by: Alexey Dobriyan <adobriyan@sw.ru>
Acked-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch removes interrupt priority tables from the intc code.
Optimal priority assignment varies with embedded application anyway,
so keeping the interrupt priority tables together with cpu-specific
code doesn't make sense.
The function intc_set_priority() should be used instead to set the
desired interrupt priority level.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch provides specific clock support for the SH7712.
Signed-off-by: Andrew Murray <amurray@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds support for the SH7263 (SH-2A) CPU.
This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.
No visibly nasty surprises, yet..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
There is no need for kobject_unregister() anymore, thanks to Kay's
kobject cleanup changes, so replace all instances of it with
kobject_put().
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Stop using kobject_register, as this way we can control the sending of
the uevent properly, after everything is properly initialized.
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The ST40 stuff in-tree hasn't built for some time, and hasn't been
updated for over 3 years. ST maintains their own out-of-tree changes
and rebases occasionally, and that's ultimately where all of the ST40
users go anyways.
In order for the ST40 code to be brought up to date most of the stuff
removed in this changeset would have to be rewritten anyways, so there's
very little benefit in keeping the remnants around either.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This was all reworked some time ago, the old debug_enter was ripped
out with everything going through a debug trap jump table instead.
Kill off the debug_enter target and reference kgdb_handle_exception
directly.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Currently clock propagation only works for one level, but we have some
clocks which need to propagate multiple levels, so make this recursive.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Not all of the SH-X2 URAM blocks are mapped in the same place,
SH7785 happens to map it on the opposite end of the address space
from SH7722, correct the addresses.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.
This also allows for some header tidying.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
There was some debug code left in here that caused the pin changes
to never be hit. Kill that off, and all is well.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The probing logic works for both URAM and L2, with no way to
distinguish between the two. Disable the probing for now and
let the CPU subtypes that have this in a real L2 configuration
explicitly say so.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds basic support for SH-X3 SMP (4 CPUs).
More IPI and cache debugging is necessary, mostly interfacing the
d-cache coherency and the I-cache broadcast invalidates. Only for
testing at present!
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
There was a very preliminary bunch of SMP code scattered around for the
SH7604 microcontrollers from way back when, and it has mostly suffered
bitrot since then. With the tree already having been slowly getting
prepped for SMP, this plugs in most of the remaining platform-independent
bits.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements initial support for the SMP INTC (particularly
INTC2) controllers.
These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch contains the following fixes and improvements:
- Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780.
- Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking.
- Good old IRQ_MODE_IRLnnnn should not register any intc controller.
- plat_irq_setup_pins() now selects IRL or IRQ mode.
- the holding function is now disabled using ICR0.
By default all external pin interrupts are disabled.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
All processor specific interrupt code is now converted to make use
of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is
because of that pointless.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CC arch/sh/kernel/cpu/sh4/sq.o
arch/sh/kernel/cpu/sh4/sq.c: In function 'sq_flush_range':
arch/sh/kernel/cpu/sh4/sq.c:65: warning: passing argument 1 of 'prefetch' discards qualifiers from pointer target type
This didn't actually need to be volatile in the first place, so just
kill off the qualifier entirely.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for sh7206
from ipr to intc. New vectors are also added to match the information
provided by the datasheet.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for sh7619
from ipr to intc. New vectors are also added to match the information
provided by the datasheet.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch makes sure the serial port interrupt irqs matches the
datasheet. Only irqs for SCIF1 are changed. While at some cosmetic
spaces are added.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch contains various intc fixes for problems reported by
Markus Brunner on the linuxsh-dev mailing list:
http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1
Apart from added comments, the fixes are:
- add intc_set_priority() function prototype to hw_irq.h
- fix off-by-one error in intc_set_priority()
- make sure _INTC_WIDTH() is set for primary priority masking
Big thanks to Markus for finding these problems. Version two fixes
a compile error and an inverted primary check.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the intc core improved it is now possible to put the intc data
structures in the initdata section.
Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the intc dual prio register support in place it is now possible
to add the ipi vectors to x3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch reworks the intc core, implementing the following features:
- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
__initdata
- Save memory - allocated memory footprint is smaller than intc
structures
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This makes sure the function prototype for setup_bootmem_node() gets
included. The file setup-shx3.c does not compile otherwise for
CONFIG_NUMA=n.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds support for the SH7720 (SH3-DSP) CPU.
Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
IRL doesn't always define sense registers, so don't bother trying to
iterate through the table. This ended up causing an oops on SH-X3
when using IRL mode.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
There is no point in keeping around the now unused intc2 code.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds single bitmap register support to intc. The current
code only handles 16 and 32 bit registers where a set bit means
interrupt enabled, but this is easy to extend in the future.
The INTC_IRQ() macro is also added to provide a way to hook in
interrupt controllers for FPGAs in boards or companion chips.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes redundant interrupt code for the shmin board which
is using a sh770x processor and 4 IRQ lines as individual interrupts
(IRQ-mode).
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes redundant board specific interrupt code for boards
using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode"
aka IRLM.
Three boards are affected: sh03, snapgear and titan.
The right way to do this is to use cpu specific code provided by intc.
A nice side effect is that sh03 now compiles, board not BROKEN any more.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
All SH-4 parts have a 4-digit year, while the SH-3 parts typically
only use a 2-digit one. The SH7705, SH7710, and SH7712 SH-3 parts
however opted to extend it to 4-digit and still look and act like
an SH-3 RTC in all other ways.
This adds a capability flag (RTC_CAP_4_DIGIT_YEAR) that these
corner-case CPU subtypes can set in their platform data and cleans
up some of the ifdef mess in the driver as a result.
Reported-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for x3 from
intc2 to intc. New vectors are also added to match the preliminary
information.
Use plat_irq_setup_pins() to select between IRQ and IRL mode for IRQ0-3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The intc tables for sh3 currently contain a typo where the bit
fields in IPRD are mixed up for IRQ4 and IRQ5. This patch makes
sure the correct bit fields are used - all according to the
datasheets.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for sh7760
from ipr + intc2 to intc. New vectors are also added to match the
information provided by the datasheet.
Vectors for IRQ4-IRQ7 are enabled by default. Use plat_irq_setup_pins()
if pins IRL0-3 should be used in IRLM mode.
The patch also adds the SIM block to the serial port platform data.
Version two of this patch fixes MMCIF problems reported by Manuel Lauss.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for sh7785
from intc2 to intc. New vectors are also added to match the information
provided by the datasheet.
No IRQ/IRL pin vectors are enabled by default. Use plat_irq_setup_pins()
to select between IRL and IRQ mode.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This reworks the cache mode configuration in Kconfig, and allows for
explicit selection of write-back/write-through/off configurations.
All of the cache flushing routines are optimized away for the off
case.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch makes sure that the sh7710 specific ipsec vector is missing
if building for a sh7712. All according to the datasheet.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds a few missing vectors for sh7707. The only interrupt
controller differences between sh7707 and sh7709 seem to be added
vectors for one LCD controller and two PCMCIA slots.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch unifies the cpu specific interrupt setup code for
sh7706, sh7707, sh7708 and sh7709 and moves the code into a new
file called setup-sh770x.c. It makes sense to share the setup code
between these processors because most hardware blocks are identical
from a software point of view. With this patch the sh770x processors
now have a complete set of vectors that match with the information
provided by the data sheets. This is a big improvement for sh7708.
Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
This patch also unifies the platform device setup code which means
that the rtc driver now has platform data for all sh770x processors.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code
for sh7710 from ipr to intc. While at it new vectors are added
to match the information provided by the datasheet. Version two
simplifies the Kconfig part.
Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
This patch also adds sh7710 specific platform data for the rtc
driver. The base address of SCIF1 is adjusted to match the
datasheet.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific interrupt setup code for
sh7705 from ipr to intc. While at it new vectors are added to
match the information provided by the datasheet.
Vectors for IRQ4 and IRQ5 are enabled by default.
Use plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
This patch also adds sh7705 specific platform data for the rtc driver.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds a plat_irq_setup() symbol for sh4-202. Without
this fix it is impossible to build a working kernel using the
microdev_defconfig.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
In the SH-3/4 TLB access violation path we were enabling IRQs before
the call in to trace_hardirqs_on(), which ended up triggering:
if (DEBUG_LOCKS_WARN_ON(!irqs_disabled()))
return;
in kernel/lockdep.c:2031. Fix this up by removing the early re-enable,
we were already re-enabling IRQs post-trace_hardirqs_on() already, so
the semantics are now as was initially intended.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes old dead code:
- kill off sh7300 cpu support
- get rid of broken solution engine 7300 board support
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes old dead code:
- kill off sh73180 cpu support
- get rid of broken solution engine 73180 board support
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The code in arch/sh/kernel/cpu/irq/pint.c doesn't compile, so let's
get rid of it to make space for a future pint implementation on top
of intc.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific 7750 setup code to use the
new intc controller. Many new vectors are added and multiple
processor variants including 7091, 7750, 7750s, 7750r, 7751 and
7751r should all have the correct vectors hooked up.
IRLM interrupts can be enabled using ipr_irq_enable_irlm() which
now is marked as __init.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that the round_rate() op is supported, hook it up on SH7722
for the FRQCR (CPU, PCLK, etc.) clocks.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This is an optional component of the clock framework. However,
as we're going to be using this in the cpufreq drivers, add
support for it to the framework.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific 7780 setup code to use the
new intc controller. Many new vectors are added and also support for
external interrupt sense configuration. So with this patch it is now
possible to configure external interrupt pins as edge or level
triggered using set_irq_type().
No external interrupts are registered by default.
Use plat_irq_setup_pins() to select between IRQ or IRL mode.
This patch also fixes the Alarm IRQ for the RTC.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch improves intc group support, ie it makes it possible to
group interrupts together and mask / unmask the entire group. This
also works with priorities, so setting a priority for an entire group
is also possible. This patch is needed to properly support certain
processors such as the 7780.
Fixes for NULL pointers in DECLARE_INTC_DESC() are also included.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch unifies the cpu specific interrupt setup functions for
interrupt controller blocks such as ipr, intc2 and intc. There is no
point in having separate functions for each interrupt controller, so
let's clean this up.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch converts the cpu specific 7722 setup code to use the
new intc controller. Many new vectors are added and also support
for external interrupt sense configuration. So with this patch
it is now possible to configure external interrupt pins as edge
or level triggered using set_irq_type().
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This is the second version of the shared interrupt controller patch
for the sh architecture, fixing up handling of intc_reg_fns[].
The three main advantages with this controller over the existing
ones are:
- Both priority (ipr) and bitmap (intc2) registers are
supported
- External pin sense configuration is supported, ie edge
vs level triggered
- CPU/Board specific code maps 1:1 with datasheet for
easy verification
This controller can easily coexist with the current IPR and INTC2
controllers, but the idea is that CPUs/Boards should be moved over
to this controller over time so we have a single code base to
maintain.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch contains two serial port related fixes for sh7722:
- Make sure the irqs for the first serial port is correct
- Add the second and third serial port to the platform data
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Slab destructors were no longer supported after Christoph's
c59def9f22 change. They've been
BUGs for both slab and slub, and slob never supported them
either.
This rips out support for the dtor pointer from kmem_cache_create()
completely and fixes up every single callsite in the kernel (there were
about 224, not including the slab allocator definitions themselves,
or the documentation references).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
We need to know the CPU ID in order to calculate the mask and ack
registers effectively. Stub this in for UP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch reworks the ipr code by grouping the offset array together
with the ipr_data structure in a new data structure called ipr_desc.
This new structure also contains the name of the controller in struct
irq_chip. The idea behind putting struct irq_chip in there is that we
can use offsetof() to locate the base addresses in the irq_chip
callbacks. This strategy has much in common with the recently merged
intc2 code.
One logic change has been made - the original ipr code enabled the
interrupts by default but with this patch they are all disabled by
default.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Magnus Damm