Commit graph

81 commits

Author SHA1 Message Date
David Daney
0c2f4551df MIPS: Decode core number for R2 CPUs.
The struct cpuinfo_mips.core field should be populated with the
physical core number.  For R2 CPUs, this is carried in the low 10 bits
of Ebase.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1505/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05 13:26:26 +01:00
Lars-Peter Clausen
83ccf69d8f MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip
Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05 13:26:12 +01:00
Kevin Cernekee
0103d23f44 MIPS: nofpu and nodsp only affect CPU0
The "nofpu" and "nodsp" kernel command line options currently do not
affect CPUs that are brought online later in the boot process or
hotplugged at runtime.  It is desirable to apply the nofpu/nodsp options
to all CPUs in the system, so that surprising results are not seen when
a process migrates from one CPU to another.

[Ralf: Moved definitions of mips_fpu_disabled, fpu_disable,
mips_dsp_disabled and dsp_disable from setup.c to cpu-probe.c to allow
making mips_fpu_disabled and mips_dsp_disabled static.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1169/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-21 21:31:17 +01:00
David Daney
6f329468f3 MIPS: Give Octeon+ CPUs their own cputype.
This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:26 +01:00
David Daney
368bf8ef30 MIPS: Set __elf_platform for Octeon.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:20 +01:00
David Daney
874fd3b5ac MIPS: Allow the auxv's elf_platform entry to be set.
The userspace runtime linker uses the elf_platform to find the libraries
optimized for the current CPU archecture variant.  First we need to allow it
to be set to something other than NULL.  Follow-on patches will set some
values for specific CPUs.

GLIBC already does the right thing.  The kernel just needs to supply good
data.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/891/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:20 +01:00
Roel Kluin
2fe0626080 MIPS: Cleanup switches with cases that can be merged
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
To: linux-mips@linux-mips.org
To: Andrew Morton <akpm@linux-foundation.org>
To: LKML <linux-kernel@vger.kernel.org>
Patchwork: http://patchwork.linux-mips.org/patch/860/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:14 +01:00
David Daney
1b362e3e35 MIPS: Decode c0_config4 for large TLBs.
For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/866/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:13 +01:00
David Daney
5b7efa898b MIPS: Don't probe reserved EntryHi bits.
The patch that adds cpu_probe_vmbits is erroneously writing to reserved
bit 12.  Since we are really only probing high bits, don't write this bit
with a one.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: Guenter Roeck <guenter.roeck@ericsson.com>
Patchwork: http://patchwork.linux-mips.org/patch/949/
Acked-by: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-10 22:15:46 +01:00
Guenter Roeck
91dfc423cc MIPS: 64-bit: Detect virtual memory size
Linux kernel 2.6.32 and later allocate address space from the top of the
kernel virtual memory address space.

This patch implements virtual memory size detection for 64 bit MIPS CPUs
to avoid resulting crashes.

Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/935/
Reviewed-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-02 19:56:23 +01:00
Wu Zhangjin
f8ede0f700 MIPS: Loongson 2F: Add CPU frequency scaling support
Loongson 2F supports CPU clock scaling. When put it into wait mode by
setting the frequency as ZERO it will stay in this mode until an external
interrupt wakes the CPU again.

To enable clock scaling support, an external timer of a known stable rate
is required.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cpufreq@vger.kernel.org,
Cc: Dave Jones <davej@redhat.com>,
Cc: Dominik Brodowski <linux@dominikbrodowski.net>,
Cc: yanh@lemote.com
Cc: huhb@lemote.com,
Patchwork: http://patchwork.linux-mips.org/patch/660/
Patchwork: http://patchwork.linux-mips.org/patch/751/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-17 01:57:20 +00:00
Chris Dearman
a074f0e89f MIPS: SPRAM: Clean up support code a little
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:05 +01:00
Maxime Bizon
0de663ef86 MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.
Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:52 +02:00
Ralf Baechle
982f6ffeee MIPS: Remove useless zero initializations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:51 +02:00
Manuel Lauss
2882b0c63a MIPS: Alchemy: get rid of allow_au1k_wait
Eliminate the 'allow_au1k_wait' variable.  MIPS kernel installs the
Alchemy-specific wait code before timer initialization;  if the C0
timer must be used for timekeeping the wait function is set to NULL
which means no wait implementation is available.

As a sideeffect, the 'wait instruction available' output in
/proc/cpuinfo now correctly indicates whether 'wait' is usable.

Run-tested on DB1200.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:50 +02:00
Ralf Baechle
631330f584 MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
Some of the were relying into smp.h being dragged in by another header
which of course is fragile.  <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
Manuel Lauss
270717a8a0 MIPS: Alchemy: unify CPU model constants.
This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.

All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization.  The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.

Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30 14:49:45 +02:00
Shinya Kuribayashi
a644b2774d MIPS: NEC VR5500 processor support fixup
Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-11 21:11:07 +01:00
Manuel Lauss
0c694de12b MIPS: Alchemy: RTC counter clocksource / clockevent support.
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device.  As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.

If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:27 +00:00
David Daney
0dd4781bca MIPS: Add Cavium OCTEON processor constants and CPU probe.
Add OCTEON constants to asm/cpu.h and asm/module.h.

Add probe function for Cavium OCTEON CPUs and hook it up.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:22 +00:00
Ralf Baechle
cea7e2dfde MIPS: Sort out CPU type to name translation.
As noticed by David Daney <ddaney@caviumnetworks.com>, the old long switch
statement did not comply with the Linux C coding style.  It was also yet
another place of code to be changed when adding a new processor type
leading to annoying bugs for example in /proc/cpuinfo.

Fixed by moving the setting of the CPU type string into the core of the
probing code and a few BUG_ON() test to ensure the CPU probing code indeed
did its job and removing multiple now redundant tests.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-30 14:44:34 +00:00
Ralf Baechle
558ce12494 MIPS: Probe for watch registers on cores of all vendors, not just MTI.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: David Daney <ddaney@caviumnetworks.com>
2008-10-30 14:44:34 +00:00
David Daney
654f57bfb4 MIPS: Probe watch registers and report configuration.
Probe for watch register characteristics, and report them in /proc/cpuinfo.

Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11 16:18:56 +01:00
Kevin D. Kissell
8531a35e5e [MIPS] SMTC: Fix SMTC dyntick support.
Rework of SMTC support to make it work with the new clock event system,
allowing "tickless" operation, and to make it compatible with the use of
the "wait_irqoff" idle loop.  The new clocking scheme means that the
previously optional IPI instant replay mechanism is now required, and has
been made more robust.

Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Atsushi Nemoto
c65a5480ff [MIPS] Fix potential latency problem due to non-atomic cpu_wait.
If an interrupt happened between checking of NEED_RESCHED and WAIT
instruction, adjust EPC to restart from checking of NEED_RESCHED.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-21 14:52:57 +02:00
Daniel Laird
a92b05880d [MIPS] Move arch/mips/philips to arch/mips/nxp
Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:26 +01:00
Ralf Baechle
39b8d52542 [MIPS] Add support for MIPS CMP platform.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:26 +01:00
Chris Dearman
0b6d497fcb [MIPS] Basic SPRAM support
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:23 +01:00
Ralf Baechle
234fcd1484 [MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12 14:14:41 +00:00
Manuel Lauss
237cfee1db [MIPS] Alchemy: Au1210/Au1250 CPU support
This patch adds IDs for new Au1200 variants: Au1210 and Au1250.
They are essentially identical to the Au1200 except for the Au1210
which has a different SoC-ID in the PRId register [bits 31:24].
The Au1250 is a "Au1200 V0.2".

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:59 +00:00
Ralf Baechle
f6771dbb27 [MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Franck Bui-Huu
dec8b1ca99 [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:18 +01:00
Ralf Baechle
9966db25de [MIPS] Make facility to convert CPU types to strings generally available.
So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:17 +01:00
Ralf Baechle
641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:05 +01:00
Aurelien Jarno
1c0c13eb93 [MIPS] Add support for BCM47XX CPUs.
Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
    
It originally comes from the OpenWrt patches.
    
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:02 +01:00
Ralf Baechle
50da469a79 [MIPS] 20Kc: Disable use of WAIT instruction.
Another issue with 20Kc's WAIT, waiting for more details.  With the
2.6.23 release immindent simply disable the use of WAIT instead of a
more fancy workaround.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-14 19:08:43 +01:00
Ralf Baechle
5a81299928 [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20 18:57:39 +01:00
Marc St-Jean
9267a30d1d [MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:33:03 +01:00
Fuxin Zhang
2a21c7300b [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:33:02 +01:00
Ralf Baechle
a36920200c [MIPS] Enable support for the userlocal hardware register
Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:33:02 +01:00
Ralf Baechle
4b3e975e4a [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores
The idle loop goes to sleep using the WAIT instruction if !need_resched().
This has is suffering from from a race condition that if if just after
need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
we've just completed the test so go to sleep anyway.  This would be
trivial to fix by just disabling interrupts during that sequence as in:

        local_irq_disable();
        if (!need_resched())
                __asm__("wait");
        local_irq_enable();

but the processor architecture leaves it undefined if a processor calling
WAIT with interrupts disabled will ever restart its pipeline and indeed
some processors have made use of the freedom provided by the architecture
definition.  This has been resolved and the Config7.WII bit indicates that
the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
74K starting revision 2.1.0 so enable the use of WAIT with interrupts
disabled for 74K based on a c0_prid of at least that.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-06 16:17:11 +01:00
Ralf Baechle
c8eae71dc8 [MIPS] 20K: Handle WAIT related bugs according to errata information
We used to avoid the WAIT entirely on the 20K but really only need to do
this on early revs of the 20K.  Without this a 20K was a bit of a
power hog.  Well, in the lower power power hog category ;-)

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-26 19:57:33 +02:00
Atsushi Nemoto
f49a747c4a [MIPS] Make some __setup functions static
This fixes some sparse warnings. ("warning: symbol 'foo' was not
declared. Should it be static?")

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-20 01:26:41 +00:00
Ralf Baechle
5759906ca9 [MIPS] Include <asm/bugs> to for declaration of check_bugs32.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-18 21:31:36 +00:00
Ralf Baechle
e0daad449c [MIPS] Whitespace cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:19 +00:00
Ralf Baechle
c237923009 [MIPS] Don't print presence of WAIT instruction on bootup.
Not useful and quite a big of noise on bootup of large systems.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:44 +00:00
Ralf Baechle
441ee341ad [MIPS] Fix RM9000 wait instruction detection.
Only revisions < 4.0 don't have a functional wait instruction.

From Thomas Koeller (Thomas.Koeller@baslerweb.com).

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-09 23:20:45 +01:00
Atsushi Nemoto
60a6c3777e [MIPS] Reduce race between cpu_wait() and need_resched() checking
If a thread became runnable between need_resched() and the WAIT
instruction, switching to the thread will delay until a next interrupt.
Some CPUs can execute the WAIT instruction with interrupt disabled, so
we can get rid of this race on them (at least UP case).

Original Patch by Atsushi with fixing up for MIPS Technology's cores by
Ralf based on feedback from the RTL designers.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:40 +01:00
Thiemo Seufer
c36cd4bab5 [MIPS] Save 2k text size in cpu-probe
The appended patch drops the inline for decode_configs, this saves about
2k of text size.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:01 +01:00
Thiemo Seufer
3a01c49ad8 [MIPS] Uses MIPS_CONF_AR instead of magic constants.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:01 +01:00