The dependency on MFD_WM8994 rather than I2C went awry.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
The WM8994 is a highly integrated ultra-low power hi-fi audio subsystem
designed for smartphones and other portable devices rich in multimedia
features. It provides advanced digital mixing facilities enabling low
power high quality interconnection of CPU, baseband and other audio
sources through flexible digital and analogue routing, and integrates
a class W headphone driver and stereo class D speaker drivers.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Use a two code correction for optimal performance.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Perform DC servo offset calibration using a series update sequence
rather than startup update sequence, tuning the configuration of the
WM8993 DC servo to make best use of this.
Also introduce currently unused data allowing us to correct for
any systematic errors in the DC servo calibration results and an
alternative startup path for the headphone output which performs
better with some chip revisions. The alternative setup sequence is
enabled for WM8993.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
In case, if OPCLK is not used, and PLL is used for driving the codec, the
choice of PLL output frequency could result in a needlessly imprecise
system clock frequency. Use an iterative process to select a precise
configuration.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
wm8974 and wm8978 codec drivers control DAC and ADC oversampling rates in their
.set_clkdiv() methods, which is wrong, because these are simple boolean
switches and not clock dividers. Move these bits to sound controls. Also remove
manual configuration of the MCLK divider in wm8978, since it is configured
automatically.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tests showed, that bit 6 of the WM8978_POWER_MANAGEMENT_2 register of wm8978
affects codec clocks. Being useless for suspend / resume, it cannot be used in
bias-level control either. Remove this bit handling.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Commit e9ff5eb2 (Fixing infinite loop in resume path) uses wrong AIC23
register in resume function because of which register writes happen
on some non-existing registers.
Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Also renames a few things to make volumes and switches match up in
alsamixer.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
The version isn't being updated or used, the kernel revision
tracking is enough.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Change the legacy default register configuration, which left some
internal components on.
Now we have either DAPM, or other ways to control these bits,
so there is no need to enable them by default.
The affected parts:
Disable ADCL and ADCR
Disable ARXL2 and ARXR2 analog PGA (playback)
Disable APLL by default
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The WM8978 codec from Wolfson Microelectronics is very similar to
wm8974, but is stereo and also has some differences in pin configuration
and internal signal routing. This driver is based on wm8974 and takes
the differences into account.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Barry Song <Barry.Song@analog.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Barry Song <Barry.Song@analog.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
tests show frequent suspend/resume(frequent poweroff/on ad1836 internal
components) maybe make ad1836 clock mode wrong sometimes after wakeup.
This patch reset/restore ad1836 clock mode while executing PM, then
ad1836 can always resume to right clock status.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Remember to free the temporary register-cache.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
This provides a small power saving when audio is inactive.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Add possibility to configure the burst mode BCLK divider through platform
data structure.
The BCLK divider changes the actual speed of the serial bus in burst mode,
which is faster than the sampling frequency of the running stream.
In this way platforms can experiment with the optimal burst speed without
the need to modify the codec driver itself.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The BCLK divider was not configured in case of mode7.
This leads to unpredictable behavior when switching between FIFO modes.
Configure the BCLK divider depending on the fifo_mode (FIFO is in use,
or FIFO bypass).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Set the prefill number of samples as the same as the lower
threshold in mode7.
In this way the codec will read the same amount of data on
startup and during the running playback.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For setups with variable MCLKs, the current logic of limiting the
available sampling rates at startup time is not sufficient. We need to
be able to change the setting at a later point, and so the codec must
offer all possible rates until the hw_params are given.
This patches allows that by passing 0 as 'freq' argument to
cs4270_set_dai_sysclk().
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The transmitter supports all sample rates up to 192KHz, so the driver
should not give a limit.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The codec structure initialization statements should be
separated by semicolons.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
tpa6140a2 uses different names for the regulators.
Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
We need to set the LRCLK inversion bit to select DSP mode.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: stable@kernel.org
Initialize the glue by calling snd_soc_new_ac97_codec() as is done
in other ASoC AC97 codecs. Fixes an oops caused by dereferencing
uninitialized members in snd_soc_new_pcms().
Run-tested on Au1250.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Better integration of the core with the device model means that we now
no longer get the ASoC suspend and resume callbacks without the card
having been set up.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
The currently available FIFO modes (mode1 and mode7) require master
mode from the codec.
Do not allow the slave configuration when the FIFO is in use.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mode 7 of tlv320dac33 operates in the following way:
The codec is in master mode.
Host configures upper and lower thresholds in tlv320dac33
During playback the codec will clock in the data until the
upper threshold is reached in FIFO. At this point the codec
stops the colocks on the serial bus.
When the FIFO fill is reaching the lower threshold limit the
codec will enable the clocks on the serial bus, and clocks
in data till the upper threshold is reached.
In this mode, we can also request interrupts for threshold
events (upper, lower and alarm), which could be used for
power management.
At this point the interrupts are not enabled for this mode,
but it can be taken into use in the future, when the surrounding
code makes it possible to use it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.oc.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Use switch instead of if statements to configure FIFO bypass
and mode1.
With this change adding new FIFO mode is going to be easier,
and cleaner.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Ensure that the code is going to be readable, when new FIFO modes
are introduced later.
Move the prefill and playback state handling to inlined
functions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In order to have support for more FIFO modes supported by
tlv320dac33, the switch for enabling/disabling the FIFO
use has to be replaced with an enum.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
PM architecture of ad1938 is simple, we don't need a bundle of functions like
ad1938_pll_powerctrl, ad1938_set_bias_level for only PLL. A dapm supply will
handle on/off of PLL.
Since soc-core can poweron/off PLL on-demand, we don't need to poweron/off PLL
in suspend/resume entries too.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Barry Song <21cnbao@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tests show frequent suspend/resume(frequent poweroff/on ad1836 internal
components) maybe make ad1836 clock mode wrong sometimes after wakeup.
This patch reset/restore ad1836 clock mode while executing PM, then
ad1836 can always resume to right clock status.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mark Brown