Commit graph

914 commits

Author SHA1 Message Date
Laszlo Attila Toth
4a19ec5800 [NET]: Introducing socket mark socket option.
A userspace program may wish to set the mark for each packets its send
without using the netfilter MARK target. Changing the mark can be used
for mark based routing without netfilter or for packet filtering.

It requires CAP_NET_ADMIN capability.

Signed-off-by: Laszlo Attila Toth <panther@balabit.hu>
Acked-by: Patrick McHardy <kaber@trash.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-01-31 19:27:19 -08:00
Dmitri Vorobiev
bbdda5e1fe [MIPS] Malta, Atlas: move an extern function declaration to the header file
This was compile-tested using default configs for the boards
affected by this change.

This patch does not introduce any functional changes.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:05 +00:00
Dmitri Vorobiev
1997267072 [MIPS] Malta, Atlas, Sead: remove an extern from .c files
This patch moves the "extern" declaration for the function
mips_reboot_setup() from the board setup .c files to the
header file include/asm-mips/mips-boards/generic.h.

This fixes a warning produced by the checkpatch.pl script.

No functional changes introduced.

This was compile-tested by building the kernel for all
three boards affected by this change. All builds finished
successfully.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:04 +00:00
Ralf Baechle
302922e5f6 [MIPS] Qemu: Remove platform.
The Qemu platform was originally implemented to have an easily supportable
platform until Qemu reaches a state where it emulates a real world system.
Since the latest release Qemu is capable of emulating the MIPSsim and
Malta platforms, so this goal has been reached.  The Qemu plaform is also
rather underfeatured so less useful than a Malta emulation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:02 +00:00
Ralf Baechle
2d47c58efa [MIPS] Delete CONFIG_MSP_FPGA
Originally noticed by Jiri Olsa <olsajiri@gmail.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:01 +00:00
Yoichi Yuasa
71466dd477 [MIPS] remove unneeded button check for reset
Removed unneeded button check for reset.
Because, the Cobalt has power switch.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:00 +00:00
Yoichi Yuasa
c9662341f8 [MIPS] time: remove unused mips_timer_state()
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:00 +00:00
Ralf Baechle
ae0c69acd6 [MIPS] fixmap: delete unused __set_fixmap, set_fixmap and set_fixmap_nocache
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:15:00 +00:00
Thomas Bogendoerfer
231a35d372 [MIPS] RM: Collected changes
- EISA support for non PCI RMs (RM200 and RM400-xxx). The major part
  is the splitting of the EISA and onboard ISA of the RM200, which
  makes the EISA bus on the RM200 look like on other RMs.
- 64bit kernel support
- system type detection is now common for big and little endian
- moved sniprom code to arch/mips/fw
- added call_o32 function to arch/mips/fw/lib, which uses a private
  stack for calling prom functions
- fix problem with ISA interrupts, which makes using PIT clockevent
  possible

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:59 +00:00
Manuel Lauss
237cfee1db [MIPS] Alchemy: Au1210/Au1250 CPU support
This patch adds IDs for new Au1200 variants: Au1210 and Au1250.
They are essentially identical to the Au1200 except for the Au1210
which has a different SoC-ID in the PRId register [bits 31:24].
The Au1250 is a "Au1200 V0.2".

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:59 +00:00
Thomas Bogendoerfer
e2defae5a9 [MIPS] IP28 support
Add support for SGI IP28 machines (Indigo 2 with R10k CPUs)
This work is mainly based on Peter Fuersts work.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:58 +00:00
Ralf Baechle
81149be113 [MIPS] Remove CONFIG_SIBYTE_PT{1120,1125,SWARM}
According to Broadcom the PT systems are production test systems which
never reached customers so no need to keep the fragmentary support we
currently have.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:58 +00:00
Thomas Bogendoerfer
930bff8822 [MIPS] IP28: added cache barrier to assembly routines
IP28 needs special treatment to avoid speculative accesses. gcc
takes care for .c code, but for assembly code we need to do it
manually.

This is taken from Peter Fuersts IP28 patches.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:58 +00:00
Atsushi Nemoto
2064ba23e5 [MIPS] TXx9 watchdog support for rbhma3100,rbhma4200,rbhma4500
This patch adds support for txx9wdt driver to rbhma3100, rbhma4200 and
rbhma4500 platform.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:58 +00:00
Thomas Bogendoerfer
68efdb81c6 [MIPS] IP22/IP28: fix extracting board/chip rev
Taken from Peter Fuersts IP28 patches

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:58 +00:00
Thomas Bogendoerfer
e9c33572a9 [MIPS] Use real cache invalidate
R10k non coherent machines need a real dma cache invalidate to get rid of
speculative stores in cache.  For other machines this promises a slight
speedup.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:57 +00:00
Ralf Baechle
87353d8ac3 [MIPS] SMP: Call platform methods via ops structure.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:57 +00:00
Ralf Baechle
0ab7aefc4d [MIPS] MT: Scheduler support for SMT
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:57 +00:00
Andrew Sharp
48ef2626ae [MIPS] Put cast inside macro instead of all the callers
Since all the callers of the PHYS_TO_XKPHYS macro call with a constant,
put the cast to LL inside the macro where it really should be rather
than in all the callers.  This makes macros like PHYS_TO_XKSEG_UNCACHED
work without gcc whining.

Signed-off-by: Andrew Sharp <andy.sharp@onstor.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:55 +00:00
Yoichi Yuasa
7f3f490061 [MIPS] remove unused mips_machtype
Removed unused mips_machtype.  These are only set but not used.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:55 +00:00
Christoph Hellwig
417345d8f5 [MIPS] CFE: Make code remotely resemble Linux code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:55 +00:00
Maciej W. Rozycki
619b6e18fc [MIPS] R4000/R4400 daddiu erratum workaround
This complements the generic R4000/R4400 errata workaround code and adds 
bits for the daddiu problem.  In most places it just modifies handwritten 
assembly code so that the assembler is allowed to use a temporary register 
as daddiu may now be treated as a macro that expands to a sequence of li 
and daddu.  It is the AT register or, where AT is unavailable or used 
explicitly for another purpose, an explicitly-named register is selected, 
using the .set at=<reg> feature added recently to gas.  This feature is 
only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the 
workaround remains disabled, the required version of binutils stays 
unchanged.

 Similarly, daddiu instructions put in branch delay slots in noreorder 
fragments are now taken out of them and the assembler is allowed to 
reorder them itself as possible (which it does making the whole idea of 
scheduling them into delay slots manually questionable).

 Also in the very few places where such a simple conversion was not 
possible, a handcoded longer sequence is implemented.

 Other than that there are changes to code responsible for building the 
TLB fault and page clear/copy handlers to avoid daddiu as appropriate.  
These are only effective if the erratum is verified to be present at the 
run time.

 Finally there is a trivial update to __delay(), because it uses daddiu in 
a branch delay slot.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:55 +00:00
Maciej W. Rozycki
20d60d9973 [MIPS] R4000/R4400 errata workarounds
This is the gereric part of R4000/R4400 errata workarounds.  They include 
compiler and assembler support as well as some source code modifications 
to address the problems with some combinations of multiply/divide+shift 
instructions as well as the daddi and daddiu instructions.

 Changes included are as follows:

1. New Kconfig options to select workarounds by platforms as necessary.

2. Arch top-level Makefile to pass necessary options to the compiler; also 
   incompatible configurations are detected (-mno-sym32 unsupported as 
   horribly intrusive for little gain).

3. Bug detection updated and shuffled -- the multiply/divide+shift problem 
   is lethal enough that if not worked around it makes the kernel crash in 
   time_init() because of a division by zero; the daddiu erratum might 
   also trigger early potentially, though I have not observed it.  On the 
   other hand the daddi detection code requires the exception subsystem to 
   have been initialised (and is there mainly for information).

4. r4k_daddiu_bug() added so that the existence of the erratum can be 
   queried by code at the run time as necessary; useful for generated code 
   like TLB fault and copy/clear page handlers.

5. __udelay() updated as it uses multiplication in inline assembly.

 Note that -mdaddi requires modified toolchain (which has been maintained 
by myself and available from my site for ~4years now -- versions covered 
are GCC 2.95.4 - 4.1.2 and binutils from 2.13 onwards).  The -mfix-r4000 
and -mfix-r4400 have been standard for a while though.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:54 +00:00
Frank Rowand
c2a04c4f0e [MIPS] SMTC: Fix build error.
Fix compile warning (which becomes compile error due to -Werror).  Type of
argument "flags" for spin_lock_irqsave() was incorrect in some functions.

Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-22 00:35:23 +00:00
Ralf Baechle
2e4f95822c [MIPS] Cacheops.h: Fix typo.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-15 01:04:42 +00:00
Sergei Shtylyov
dd99d9661c [MIPS] Alchemy: fix PCI resource conflict
... by getting the PCI resources back into the 32-bit range -- there's no
need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI
work again while currently the kernel skips the bus scan.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-14 17:34:29 +00:00
Manuel Lauss
0f5e49a2e2 [MIPS] Alchemy: Fix Au1x SD controller IRQ
With the introduction of MIPS_CPU_IRQ_BASE, the hardcoded IRQ number of
the au1100/au1200 SD controller(s) is no longer valid.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-09 04:51:10 +00:00
Sergei Shtylyov
0e8120e094 [MIPS] Alchemy: fix IRQ bases
Do what the commits commits f3e8d1da38 and
9d360ab4a7 failed to achieve -- actually
convert the Alchemy code to irq_cpu.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-06 17:15:58 +00:00
Pavel Kiryukhin
54fd6441e0 [MIPS] Fix use of smp_processor_id() in preemptible code.
Freeing prom memory: 956kb freed
Freeing firmware memory: 978944k freed
Freeing unused kernel memory: 180k freed
BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1
caller is r4k_dma_cache_wback_inv+0x144/0x2a0
Call Trace:
 [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0
 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0
 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0
...
CONFIG_DEBUG_PREEMPT is enabled.
--
Bug cause is blast_dcache_range() in preemptible code [in
r4k_dma_cache_wback_inv()].
blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that
uses cpu_dcache_line_size(). It uses current_cpu_data that use
smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT
smp_processor_id emits BUG if we are executing with preemption
enabled.

Cpu options of cpu0 are assumed to be the superset of all processors.

Can I make the same assumptions for cache line size  and fix this
issue the following way:

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-01 00:39:37 +00:00
Thomas Bogendoerfer
68576cf122 IP22ZILOG: fix lockup and sysrq
- fix lockup when switching from early console to real console
 - make sysrq reliable
 - fix panic, if sysrq is issued before console is opened

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-29 09:24:53 -08:00
Ralf Baechle
cce335ae47 [MIPS] 64-bit Sibyte kernels need DMA32.
Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
space only the first 1GB of memory is mapped at physical addresses
below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
not be able to reach all of it.

For now this patch is good enough to keep Sibyte users happy but it seems
eventually something like swiotlb will be needed for Sibyte.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
940f6b48a1 [MIPS] Only build r4k clocksource for systems that work ok with it.
In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
5aa85c9fc4 [MIPS] Handle R4000/R4400 mfc0 from count register.
The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
2007-11-26 17:26:14 +00:00
Ralf Baechle
0f67e90e1c [MIPS] Fix possible hang in LL/SC futex loops.
The LL / SC loops in __futex_atomic_op() have the usual fixups necessary
for memory acccesses to userspace from kernel space installed:

        __asm__ __volatile__(
        "       .set    push                            \n"
        "       .set    noat                            \n"
        "       .set    mips3                           \n"
        "1:     ll      %1, %4  # __futex_atomic_op     \n"
        "       .set    mips0                           \n"
        "       " insn  "                               \n"
        "       .set    mips3                           \n"
        "2:     sc      $1, %2                          \n"
        "       beqz    $1, 1b                          \n"
        __WEAK_LLSC_MB
        "3:                                             \n"
        "       .set    pop                             \n"
        "       .set    mips0                           \n"
        "       .section .fixup,\"ax\"                  \n"
        "4:     li      %0, %6                          \n"
        "       j       2b                              \n"	<-----
        "       .previous                               \n"
        "       .section __ex_table,\"a\"               \n"
        "       "__UA_ADDR "\t1b, 4b                    \n"
        "       "__UA_ADDR "\t2b, 4b                    \n"
        "       .previous                               \n"
        : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)
        : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)
        : "memory");

The branch at the end of the fixup code, it goes back to the SC
instruction, no matter if the fault was first taken by the LL or SC
instruction resulting in an endless loop which will only terminate if
the address become valid again due to another thread setting up an
accessible mapping and the CPU happens to execute the SC instruction
successfully which due to the preceeding ERET instruction of the fault
handler would only happen if UNPREDICTABLE instruction behaviour of the
SC instruction without a preceeding LL happens to favor that outcome.
But normally processes are nice, pass valid arguments and we were just
getting away with this.

Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original
report and a test case.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
07500b0d85 [MIPS] Fix context DSP context / TLS pointer switching bug for new threads.
A new born thread starts execution not in schedule but rather in
ret_from_fork which results in it bypassing the part of the code to
load a new context written in C which are the DSP context and the
userlocal register which Linux uses for the TLS pointer.  Frequently
we were just getting away with this bug for a number of reasons:

 o Real world application scenarios are very unlikely to use clone or fork
   in blocks of DSP code.
 o Linux by default runs the child process right after the fork, so the
   child by luck will find all the right context in the DSP and userlocal
   registers.
 o So far the rdhwr instruction was emulated on all hardware so userlocal
   wasn't getting referenced at all and the emulation wasn't suffering
   from the issue since it gets it's value straight from the thread's
   thread_info.

Fixed by moving the code to load the context from switch_to() to
finish_arch_switch which will be called by newborn and old threads.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
98ce472181 [MIPS] IP32: More interrupt renumbering fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
cfb6f26035 [MIPS] Fix pcspeaker build.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Yoichi Yuasa
89becf5c0d [MIPS] Lasat: Fix overlap of interrupt number ranges.
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Ralf Baechle
f6771dbb27 [MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Ralf Baechle
efb9ca08b5 [MIPS] Change get_cycles to always return 0.
This avoids us executing an mfc0 c0_count instruction on processors which
don't have but also on certain R4000 and R4400 versions where reading from
the count register just in the very moment when its value equals
c0_compare will result in the timer interrupt getting lost.

There is still a number of users of get_cycles remaining outside the
arch code:

crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
drivers/char/hangcheck-timer.c: return get_cycles();
drivers/char/hangcheck-timer.c: printk("Hangcheck: Using get_cycles().\n");
drivers/char/random.c:  sample.cycles = get_cycles();
drivers/input/joystick/analog.c:#define GET_TIME(x)     do { x = get_cycles(); }
include/linux/arcdevice.h:          _x = get_cycles(); \
include/linux/arcdevice.h:          _y = get_cycles(); \
mm/slub.c:      if (!s->defrag_ratio || get_cycles() % 1024 > s->defrag_ratio)
mm/slub.c:      p += 64 + (get_cycles() & 0xff) * sizeof(void *);

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Ralf Baechle
74521c28e5 Use i8253.c lock for PC speaker on MIPS, too.
The Jazz machines have to use the PIT timer for dyntick and highresolution
kernels.  This may break because currently just like i386 used to do MIPS
uses two separate spinlocks in the actual PIT code and the PC speaker
code.  So switch to do it the same that x86 currently does PIT locking.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-02 19:39:18 -07:00
Ralf Baechle
72fc19ff51 [MIPS] Fix and cleanup the MIPS part of the (ab)use of CLOCK_TICK_RATE.
This is the clock rate of the i8253 PIT.  A MIPS system may not have
a PIT by the symbol is used all over the kernel including some APIs.
So keeping it defined to the number for the PIT is the only sane thing
for now.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
f6a8cc31aa [MIPS] i8253.h: Remove all i8259 related definitions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Yoichi Yuasa
9aa4cc11b2 [MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Atsushi Nemoto
d9eec1a5d6 [MIPS] time: Code cleanups
* Do not include unnecessary headers.
* Do not mention time.README.
* Do not mention mips_timer_ack.
* Make clocksource_mips static.  It is now dedicated to c0_timer.
* Initialize clocksource_mips.read statically.
* Remove null_hpt_read.
* Remove an argument of plat_timer_setup.  It is just a placeholder.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
1d0a909cfc [MIPS] time: Remove now unused local_timer_interrupt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
38760d40ca [MIPS] time: Replace plat_timer_setup with modern APIs.
plat_timer_setup is no longer getting called.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Atsushi Nemoto
229f773ef4 [MIPS] txx9tmr clockevent/clocksource driver
Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode.  The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.

Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore.  The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
8a13ecd7b2 [MIPS] IP32: Fixes after interrupt renumbering.
And general untangling.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
0d0cc920de [MIPS] time: Remove declaration of plat_timer_setup, there is no caller.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00