Commit graph

19 commits

Author SHA1 Message Date
Stephen Boyd
7fa22bd546 ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1
If an ARM system has multiple cpus in the same socket and the
kernel is booted with maxcpus=1, secondary cpus are possible but
not present due to how platform_smp_prepare_cpus() is called.
Since most typical ARM processors don't actually support physical
hotplug, initialize the present map to be equal to the possible
map in generic ARM SMP code. Also, always call
platform_smp_prepare_cpus() as long as max_cpus is non-zero (0
means no SMP) to allow platform code to do any SMP setup.

After applying this patch it's possible to boot an ARM system
with maxcpus=1 on the command line and then hotplug in secondary
cpus via sysfs. This is more in line with how x86 does things.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-07 14:45:07 +01:00
Linus Walleij
4d5336d50a ARM: 6895/1: mach-ux500: fix SMP secondary startup regression
Commit e2a083dc0da9aa6437e14811198379b18cdfa7f8
"ARM: consolidate SMP cross call implementation" broke the ux500
compilation since the smp.h header declared a function called
from headsmp.S. This fixes it up by declaring it locally instead.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-23 16:53:17 +01:00
Russell King
0f7b332f97 ARM: consolidate SMP cross call implementation
Rather than having each platform class provide a mach/smp.h header for
smp_cross_call(), arrange for them to register the function with the
core ARM SMP code instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-23 16:53:17 +01:00
Rabin Vincent
92389ca836 ux500: remove build-time changing macros
To allow the possiblity of building U8500 and U5500 support in the same
image.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
[Rebased to latest changes in Russells tree]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2011-01-10 18:34:52 +01:00
Russell King
404a02cbd2 Merge branch 'devel-stable' into devel
Conflicts:
	arch/arm/mach-pxa/clock.c
	arch/arm/mach-pxa/clock.h
2011-01-06 22:33:32 +00:00
Russell King
4073723acb Merge branch 'misc' into devel
Conflicts:
	arch/arm/Kconfig
	arch/arm/common/Makefile
	arch/arm/kernel/Makefile
	arch/arm/kernel/smp.c
2011-01-06 22:32:52 +00:00
Russell King
3705ff6da5 ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.

What happens in the normal online/offline/online cycle is:

	CPU0			CPU3
	requests boot of CPU3
	pen_release = 3
	flush cache line
				checks pen_release, reads 3
				starts boot
				pen_release = -1
	... requests CPU3 offline ...
				... dies ...
				checks pen_release, reads -1
	requests boot of CPU3
	pen_release = 3
	flush cache line
				checks pen_release, reads 3
				starts boot
				pen_release = -1

However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:

	CPU0			CPU3
	requests boot of CPU3
	pen_release = 3
	flush cache line
				checks pen_release, reads 3
				starts boot
				pen_release = -1
	... requests CPU3 offline ...
				... dies ...
				checks pen_release, reads 3
				starts boot
				pen_release = -1
	requests boot of CPU3
	pen_release = 3
	flush cache line

Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:09:13 +00:00
Russell King
2c0136dba4 ARM: SMP: consolidate trace_hardirqs_off() into common SMP code
All platforms call trace_hardirqs_off() in their secondary startup code,
so move this into the core SMP code - it doesn't need to be in the
per-platform code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:09:09 +00:00
Russell King
05c74a6cbc ARM: SMP: consolidate the common parts of smp_prepare_cpus()
There is a certain amount of smp_prepare_cpus() which doesn't belong
in the platform support code - that is, code which is invariant to the
SMP implementation.  Move this code into arch/arm/kernel/smp.c, and
add a platform_ prefix to the original function.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:09:08 +00:00
Russell King
fd778f0ad7 ARM: SMP: get rid of get_core_count()
We don't need this small function as well as scu_get_core_count()

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:08:27 +00:00
Russell King
8975b6c0fd ARM: SMP: Clean up ncores sanity checks
scu_get_core_count() never returns zero cores, so we don't need to
check and correct if ncores is zero.

Tegra was missing the check against NR_CPUS, leading to a potential
bitfield overflow if this becomes the case.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:08:27 +00:00
Russell King
bbc3d14e9a ARM: SMP: move CPU number sanity checks to smp_init_cpus()
Ensure that the number of CPUs is sanity checked before setting
the number of possible CPUs.  This avoids any chance of overflowing
the cpu_possible bitmap.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 15:08:26 +00:00
Jonas Aaberg
3c5728edbe ux500: platsmp: Fix section mismatch
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2010-12-19 21:31:49 +01:00
Russell King
384895330e ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init
We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.

Get rid of this argument, and rename to gic_secondary_init().

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:40 +00:00
Russell King
ad3b6993b9 ARM: SMP: pass an ipi number to smp_cross_call()
This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI.  Recover the SGI number via do_IPI.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-03 08:26:30 +00:00
Sundar Iyer
9d704c04ff ARM: 6391/1: ux500: add CPU hotplug support
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-19 12:14:34 +01:00
Rabin Vincent
817412d3a1 ARM: 6088/1: ux500: use UX500_* macros instead of U8500_*
So that the correct addresses get used on U5500.

Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-04 17:50:05 +01:00
Srinidhi Kasagar
8e797a7e4f ARM: 6027/1: ux500: enable l2x0 support
This enables the l2x0 support and ensures that the secondary
CPU can see the page table and secondary data at this point.

Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-04-14 16:08:10 +01:00
Srinidhi Kasagar
aa44ef4d43 ARM: 5831/1: ARM: U8500 core machine support
Adds core support for the ST-Ericsson U8500
platform. It supports memory mappings, binds to
the existing modules like GIC, SCU, TWD and
local timers and sets up the infrastructure for
the secondary core.

Reviewed-by: Alessandro Rubini <rubini@unipv.it>
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-11-28 10:22:52 +00:00