Commit graph

78 commits

Author SHA1 Message Date
David S. Miller
45b3f4cc60 [SPARC64]: virt_to_real_irq_table --> virt_irq_table
It no longer translates to "real irqs" (aka. INO buckets)
so reflect that by using a simpler name for it.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 23:52:14 -07:00
David S. Miller
256c1df36b [SPARC64]: virt_irq --> bucket mapping no longer necessary
We used to need this to compute virt_irq --> ino, but that
is no longer necessary.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 23:50:38 -07:00
David S. Miller
771823007f [SPARC64]: Kill ugly __bucket() macro.
All the users go through virt_irq_to_bucket() and essentially
want to go from a virt_irq to an INO, but we have a way
to do that already via virt_to_real_irq_table[].dev_ino.

This also allows us to kill both virt_to_real_irq() and
virt_irq_to_bucket().

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 23:41:28 -07:00
David S. Miller
bb74b734a6 [SPARC64]: Kill ugly __irq_ino() macro.
We have a place to stick INO information in the
virt_to_real_irq_table[], which is currently only used for VIRQs.
And that is readily accessible from the one __irq_ino() call site.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 23:27:48 -07:00
David S. Miller
42d5f99b1d [SPARC64]: Only use bypass accesses to INO buckets.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 23:03:21 -07:00
David S. Miller
b80e699812 [SPARC64]: Use sun4v VIRQ interfaces as intended.
We were simply concatenating the devhandle and devino and using that
as the cookie, which defeats the entire purpose of the VIRQ hypervisor
interfaces.

Now that we use physical addresses for the INO buckets, we can
allocate them dynamically for VIRQs and encode the cookies as
~__pa(bucket).  This allows us to test for and decode the cookie with
a simple:

	brlz	$reg1, 1f
	 xnor	$reg1, %g0, $reg2

sequence.

This works because bit 64 is never set in traditional
INO vectors, and it is also never set in a physical
address.  So xnor'ing the physical address of the bucket
always gives us a negative number, and thus a unique
condition we can test cheaply.

Inspired by ideas from Greg Onufer.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:16 -07:00
David S. Miller
10397e4069 [SPARC64]: Allocate ivector_table dynamically.
Shrinks kernel by 16K compared to before the IVEC physical
address changes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:16 -07:00
David S. Miller
eb2d8d6032 [SPARC64]: Access ivector_table[] using physical addresses.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:15 -07:00
David S. Miller
a650d3839e [SPARC64]: Make IVEC pointers 64-bit.
Currently we chain IVEC entries using 32-bit "pointers"
because we know that the ivector_table is in the main
kernel image, thus below 4GB.

This uses proper 64-bit pointers instead.

Whilst this bloats up the kernel image size, this sets
the infrastructure necessary to significantly shrink the
kernel size by using physical addresses and dynamically
allocating the ivector table.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:15 -07:00
David S. Miller
759f89e03c [SPARC64]: Consolidate MSI support code.
This also makes us use the MSI queues correctly.

Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt
handler.  This handler runs the MSI queue and dispatches the
virtual interrupts indicated by arriving MSIs in that MSI queue.

All of the common logic is placed in pci_msi.c, with callbacks to
handle the PCI controller specific aspects of the operations.

This common infrastructure will make it much easier to add MSG
support.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:13 -07:00
David S. Miller
9bb3c227c4 [SPARC64]: Enable MSI on sun4u Fire PCI-E controllers.
The support code is identical to the hypervisor sun4v stuff,
just replacing the hypervisor calls with register reads and
writes in the Fire controller.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:09 -07:00
David S. Miller
5f92c32936 [SPARC64]: Fix several bugs in MSI handling.
1) sun4{u,v}_build_msi() have improper return value handling.

   We should always return negative error codes, instead of
   using the magic value "0" which could in fact be a valid
   MSI number.

2) sun4{u,v}_build_msi() should return -ENOMEM instead of
   calling prom_prom() halt with kzalloc() of the interrupt
   data fails.

3) We 'remembered' the MSI number using a singleton in the
   struct device archdata area, this doesn't work for MSI-X
   which can cause multiple MSIs assosciated with one device.

   Delete that archdata member, and instead store the MSI
   number in the IRQ chip data area.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-30 23:06:51 -07:00
David S. Miller
6e69d6068c [SPARC64]: Fix type and constant sizes wrt. sun4u IMAP/ICLR handling.
Sometimes we were using 32-bit values and the top bits were
getting inadvertantly chopped off.  This will matter for the
forthcoming Fire controller MSI support.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-30 23:06:50 -07:00
David S. Miller
b434e71933 [SPARC64]: Fix memory leak when cpu hotplugging.
Every time a cpu is added via hotplug, we allocate the per-cpu MONDO
queues but we never free them up.  Freeing isn't easy since the first
cpu gets this memory from bootmem.

Therefore, the simplest thing to do to fix this bug is to allocate the
queues for all possible cpus at boot time.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-08 17:33:52 -07:00
David S. Miller
93b3238ef8 [SPARC64]: Fix virq decomposition.
The dev_handle and dev_ino fields don't match up exactly to
the traditional IMAP_IGN and IMAP_INO masks.

So store them away in a table and look them up directly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-20 17:14:55 -07:00
David S. Miller
e83fb17f9b [SPARC64]: Use KERN_ERR in IRQ manipulation error printks.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-20 17:14:46 -07:00
David S. Miller
5f7426c0e1 [SPARC64]: Tweak assertions in sun4v_build_virq().
They are too strict.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-19 21:28:43 -07:00
David S. Miller
e0204409df [SPARC64]: dr-cpu unconfigure support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16 04:05:32 -07:00
David S. Miller
b53bcb6799 [SPARC64]: Add ->set_affinity IRQ handlers.
dr-cpu unconfigure requests will walk throught he enabled
IRQs and trigger ->set_affinity so that the going-down
cpu no longer has INOs targetted to it.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16 04:05:11 -07:00
David S. Miller
5a606b72a4 [SPARC64]: Do not ACK an INO if it is disabled or inprogress.
This is also a partial workaround for a bug in the LDOM firmware which
double-transmits RX inos during high load.  Without this, such an
event causes the kernel to loop forever in the interrupt call chain
ACK'ing but never actually running the IRQ handler (and thus clearing
the interrupt condition in the device).

There is still a bad potential effect when double INOs occur,
not covered by this changeset.  Namely, if the INO is already on
the per-cpu INO vector list, we still blindly re-insert it and
thus we can end up losing interrupts already linked in after
it.

We could deal with that by traversing the list before insertion,
but that's too expensive for this edge case.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16 04:04:05 -07:00
David S. Miller
a357b8f42e [SPARC64]: Need to set state to IDLE during sun4v IRQ enable.
This fixes hypervisor console interrupts on LDOM guests.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-06-26 00:13:31 -07:00
David S. Miller
1245088400 [SPARC64]: Fix VIRQ enabling.
We were doing the wrong call to turn them on, and also
when enabling we need to forcefully set the state to IDLE.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-06-26 00:13:09 -07:00
David S. Miller
4a907dec98 [SPARC64]: Wire up cookie based sun4v interrupt registry.
This will be used for logical domain channel interrupts.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-06-13 00:01:04 -07:00
David S. Miller
5cbc307373 [SPARC64]: Use machine description and OBP properly for cpu probing.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-29 02:49:41 -07:00
David S. Miller
861fe90656 [SPARC64]: SUN4U PCI-E controller support.
Some minor refactoring in the generic code was necessary for
this:

1) This controller requires 8-byte access to the interrupt map
   and clear register.  They are 64-bits on all the other
   SBUS and PCI controllers anyways, so this was easy to cure.

2) The IMAP register has a different layout and some bits that we
   need to preserve, so use a read/modify/write when making
   changes to the IMAP register in generic code.

3) Flushing the entire IOMMU TLB is best done with a single write
   to a register on this PCI controller, add a iommu->iommu_flushinv
   for this.

Still lacks MSI support, that will come later.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-06 22:44:06 -07:00
Stephen Rothwell
6a23acf390 [SPARC64]: constify of_get_property return: arch/sparc64
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-04-26 01:54:24 -07:00
David S. Miller
777a447529 [SPARC64]: Unify timer interrupt handler.
Things were scattered all over the place, split between
SMP and non-SMP.

Unify it all so that dyntick support is easier to add.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-04-26 01:54:11 -07:00
David S. Miller
5746c99dfa [SPARC64]: virt_irq_free only needed when CONFIG_PCI_MSI
Noticed by Meelis Roos.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-26 11:35:46 -08:00
David S. Miller
35a17eb6a8 [SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.

MSIs are assosciated with MSI Queues.  MSI Queues generate interrupts
when any MSI assosciated with it is signalled.  This suggests a
two-tiered IRQ dispatch scheme:

	MSI Queue interrupt --> queue interrupt handler
		MSI dispatch --> driver interrupt handler

But we just get one-level under Linux currently.  What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.

So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.

We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available.  If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.

The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.

We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there.  This is
another ugly wart.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-10 23:50:37 -08:00
David S. Miller
68c9218694 [SPARC64] IRQ: Use irq_desc->chip_data instead of irq_desc->handler_data
Otherwise we can't use the generic MSI code.

Furthermore, properly use the {get,set}_irq_foo() abstracted
interfaces instead of direct accesses to irq_desc[]->foo.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-10 23:50:36 -08:00
David S. Miller
729e7d7e4d [SPARC64]: Minor irq handling cleanups.
Use struct irq_chip instead of hw_interrupt_type.

Delete hw_resend_irq(), totally unused.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-12-17 14:06:56 -08:00
Al Viro
63540ba369 [PATCH] sparc64 irq pt_regs fallout
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-09 14:19:07 -07:00
Al Viro
6d24c8dc2e [PATCH] sparc64 pt_regs fixes
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-08 12:32:35 -07:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
David S. Miller
24ac26d425 [SPARC64]: Let irq_install_pre_handler() get called multiple times.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-29 16:37:27 -07:00
Ingo Molnar
a53da52fd7 [PATCH] genirq: cleanup: merge irq_affinity[] into irq_desc[]
Consolidation: remove the irq_affinity[NR_IRQS] array and move it into the
irq_desc[NR_IRQS].affinity field.

[akpm@osdl.org: sparc64 build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 10:26:22 -07:00
Ingo Molnar
d1bef4ed5f [PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.

While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.

The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.

This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.

As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.

The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.

We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.

This patch:

rename desc->handler to desc->chip.

Originally i did not want to do this, because it's a big patch.  But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.

I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.

So lets get over with this quickly.  The conversion was done automatically
via scripts and converts all the code in the kernel.

This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.

[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 10:26:21 -07:00
David S. Miller
3505599615 [SPARC64]: Allow floppy driver to build modular.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-25 23:15:01 -07:00
David S. Miller
92c4e22593 [SPARC64]: Kill unused local vars in map_prom_timers().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-23 23:15:38 -07:00
David S. Miller
25c7581bcd [SPARC64]: Kill off some more prom_getproperty() remnants.
The remaining ones occur before we have imported the
device tree.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-23 23:15:36 -07:00
David S. Miller
e18e2a00ef [SPARC64]: Move over to GENERIC_HARDIRQS.
This is the long overdue conversion of sparc64 over to
the generic IRQ layer.

The kernel image is slightly larger, but the BSS is ~60K
smaller due to the reduced size of struct ino_bucket.

A lot of IRQ implementation details, including ino_bucket,
were moved out of asm-sparc64/irq.h and are now private to
arch/sparc64/kernel/irq.c, and most of the code in irq.c
totally disappeared.

One thing that's different at the moment is IRQ distribution,
we do it at enable_irq() time.  If the cpu mask is ALL then
we round-robin using a global rotating cpu counter, else
we pick the first cpu in the mask to support single cpu
targetting.  This is similar to what powerpc's XICS IRQ
support code does.

This works fine on my UP SB1000, and the SMP build goes
fine and runs on that machine, but lots of testing on
different setups is needed.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20 01:23:32 -07:00
David S. Miller
8047e247c8 [SPARC64]: Virtualize IRQ numbers.
Inspired by PowerPC XICS interrupt support code.

All IRQs are virtualized in order to keep NR_IRQS from needing
to be too large.  Interrupts on sparc64 are arbitrary 11-bit
values, but we don't need to define NR_IRQS to 2048 if we
virtualize the IRQs.

As PCI and SBUS controller drivers build device IRQs, we divy
out virtual IRQ numbers incrementally starting at 1.  Zero is
a special virtual IRQ used for the timer interrupt.

So device drivers all see virtual IRQs, and all the normal
interfaces such as request_irq(), enable_irq(), etc. translate
that into a real IRQ number in order to configure the IRQ.

At this point knowledge of the struct ino_bucket is almost
entirely contained within arch/sparc64/kernel/irq.c  There are
a few small bits in the PCI controller drivers that need to
be swept away before we can remove ino_bucket's definition
out of asm-sparc64/irq.h and privately into kernel/irq.c

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20 01:22:35 -07:00
David S. Miller
37cdcd9e82 [SPARC64]: Kill ino_bucket->pil
And reuse that struct member for virt_irq, which will
be used in future changesets for the implementation of
mapping between real and virtual IRQ numbers.

This nicely kills off a ton of SBUS and PCI controller
PIL assignment code which is no longer necessary.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20 01:21:57 -07:00
David S. Miller
6a76267f0e [SPARC64]: bp->pil can never be zero
Only pil0_dummy_bucket had a pil of zero and we just killed that
off, so we can delete all special case code that used bp->pil==0
as a way to identify a dummy bucket.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20 01:20:30 -07:00
David S. Miller
fd0504c321 [SPARC64]: Send all device interrupts via one PIL.
This is the first in a series of cleanups that will hopefully
allow a seamless attempt at using the generic IRQ handling
infrastructure in the Linux kernel.

Define PIL_DEVICE_IRQ and vector all device interrupts through
there.

Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector
the timer interrupt directly to a specific handler since the
timer interrupt is the only event that will be signaled on
PIL 14.

The irq_worklist is now in the per-cpu trap_block[].

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20 01:20:00 -07:00
Alexey Dobriyan
53b3531bbb [PATCH] s/;;/;/g
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-24 07:33:24 -08:00
Andrew Morton
394e3902c5 [PATCH] more for_each_cpu() conversions
When we stop allocating percpu memory for not-possible CPUs we must not touch
the percpu data for not-possible CPUs at all.  The correct way of doing this
is to test cpu_possible() or to use for_each_cpu().

This patch is a kernel-wide sweep of all instances of NR_CPUS.  I found very
few instances of this bug, if any.  But the patch converts lots of open-coded
test to use the preferred helper macros.

Cc: Mikael Starvik <starvik@axis.com>
Cc: David Howells <dhowells@redhat.com>
Acked-by: Kyle McMartin <kyle@parisc-linux.org>
Cc: Anton Blanchard <anton@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: William Lee Irwin III <wli@holomorphy.com>
Cc: Andi Kleen <ak@muc.de>
Cc: Christian Zankel <chris@zankel.net>
Cc: Philippe Elie <phil.el@wanadoo.fr>
Cc: Nathan Scott <nathans@sgi.com>
Cc: Jens Axboe <axboe@suse.de>
Cc: Eric Dumazet <dada1@cosmosbay.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-23 07:38:17 -08:00
Eric Sesterhenn
9132983ae1 [SPARC64]: kzalloc() conversion
this patch converts arch/sparc64 to kzalloc usage.
Crosscompile tested with allyesconfig.

Signed-off-by: Eric Sesterhenn <snakebyte@gmx.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:19 -08:00
David S. Miller
ebd8c56c5a [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.
We need to use the real hardware processor ID when
targetting interrupts, not the "define to 0" thing
the uniprocessor build gives us.

Also, fill in the Node-ID and Agent-ID fields properly
on sun4u/Safari.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:24 -08:00
David S. Miller
72aff53f1f [SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile.  We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.

This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.

In order to achieve this:

1) Change sun4v_init_mondo_queues() so that it can operate in
   several modes.

   It can allocate the queues, or install them in the current
   processor, or both.

   The boot cpu does both in it's call early on.

   Later, the boot cpu allocates the sibling cpu queue, starts
   the sibling cpu, then the sibling cpu loads them in.

2) init_cur_cpu_trap() is changed to take the current_thread_info()
   as an argument instead of reading %g6 directly on the current
   cpu.

3) Create a trampoline stack for the sibling cpus.  We do our basic
   kernel calls using this stack, which is locked into the kernel
   image, then go to our proper thread stack after taking over the
   trap table.

4) While we are in this delicate startup state, we put 0xdeadbeef
   into %g4/%g5/%g6 in order to catch accidental accesses.

5) On the final prom_set_trap_table*() call, we put &init_thread_union
   into %g6.  This is a hack to make prom_world(0) work.  All that
   wants to do is restore the %asi register using
   get_thread_current_ds().

Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else.  This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:22 -08:00