This fixes RH bugzilla #527874.
On resume the atom posting wasn't working, however vbe posting was
going fine, after 2 weeks over irc, and 8 hrs with the hardware,
I tracked it down to the memory device table and it access the MC
registers via IIO, it appears the rv515 atom iio table might not
be fully functional, so adding a readback before doing a write
either provides enough delay to make things resume correctly.
Thanks to Peng Huang at Red Hat for coming to Brisbane.
Signed-off-by: Dave Airlie <airlied@redhat.com>
An rv515 laptop I got wouldn't startup with a montior plugged in,
found the proper bug hopefully with us not turning off D2VGA
here when we should.
Signed-off-by: Dave Airlie <airlied@redhat.com>
We did this on the userspace side, but we need a similar fix for the
kernel.
Fixes LP #460664.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
AGP resume was broken since we moved to the new init path,
because we never re-enabled AGP on these systems at resume time.
This patch just calls the AGP resume call which just does the reinit
at resume time like the old path did.
Since AGP is pretty much gpu independant I did it outside
the gpu specific code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
* 'hostprogs-wmissing-prototypes' of git://git.kernel.org/pub/scm/linux/kernel/git/josh/linux-misc:
Makefile: Add -Wmising-prototypes to HOSTCFLAGS
oss: Mark loadhex static in hex2hex.c
dtc: Mark various internal functions static
dtc: Set "noinput" in the lexer to avoid an unused function
drm: radeon: Mark several functions static in mkregtable
arch/sparc/boot/*.c: Mark various internal functions static
arch/powerpc/boot/addRamDisk.c: Mark several internal functions static
arch/alpha/boot/tools/objstrip.c: Mark "usage" static
Documentation/vm/page-types.c: Declare checked_open static
genksyms: Mark is_reserved_word static
kconfig: Mark various internal functions static
kconfig: Make zconf.y work with current bison
Add more display registers save/restore to fix unstable issues
during S4 testing on Ironlake. And DPLL_B_MD should not be restored
on Ironlake.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
The master irq control in DE must be disabled before irq handling,
and enable after the process. This fixes the irq stall issue on
Ironlake.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zou, Nanhai <nanhai.zou@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (52 commits)
drm/kms: Init the CRTC info fields for modes forced from the command line.
drm/radeon/r600: CS parser updates
drm/radeon/kms: add debugfs for power management for AtomBIOS devices
drm/radeon/kms: initial mode validation support
drm/radeon/kms/atom/dce3: call transmitter init on mode set
drm/radeon/kms: store detailed connector info
drm/radeon/kms/atom/dce3: fix up usPixelClock calculation for Transmitter tables
drm/radeon/kms/r600: fix rs880 support v2
drm/radeon/kms/r700: fix some typos in chip init
drm/radeon/kms: remove some misleading debugging output
drm/radeon/kms: stop putting VRAM at 0 in MC space on r600s.
drm/radeon/kms: disable D1VGA and D2VGA if enabled
drm/radeon/kms: Don't RMW CP_RB_CNTL
drm/radeon/kms: fix coherency issues on AGP cards.
drm/radeon/kms: fix rc410 suspend/resume.
drm/radeon/kms: add quirk for hp dc5750
drm/radeon/kms/atom: fix potential oops in spread spectrum code
drm/kms: typo fix
drm/radeon/kms/atom: Make card_info per device
drm/radeon/kms/atom: Fix DVO support
...
Generally this is done at post, but might not always be done
with softboot or for connectors on docking stations.
Could probably be done once when the driver loads/resumes
rather than on each mode set.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This will be useful for mode validation and certain
atom tables.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Lots of cases were wrong or missing.
v2: rebased against drm-next
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This brings some hardware workaround for HDMI port on PCH (Ibex Peak),
which fixes unstable issues like during rotation.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.
This fixes DPLL clock issue against one monitor at 1680x1050@60hz.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Miles Lane reported the following error:
2 locks held by cat/4179:
#0: (&p->lock){+.+.+.}, at: [<c10a3884>] seq_read+0x25/0x315
#1: (&dev_priv->mm.active_list_lock){+.+...}, at: [<c119a854>]
i915_batchbuffer_info+0x2b/0x124
Pid: 4179, comm: cat Not tainted 2.6.32-rc5-git1 #2
Call Trace:
[<c104874f>] ? __debug_show_held_locks+0x1e/0x20
[<c1023fb0>] __might_sleep+0xf0/0xf7
[<c101c393>] kmap+0x17/0x58
[<c119a8d6>] i915_batchbuffer_info+0xad/0x124
[<c10a39bf>] seq_read+0x160/0x315
[<c108fb8c>] ? rw_verify_area+0x98/0xbb
[<c10a385f>] ? seq_read+0x0/0x315
[<c1090331>] vfs_read+0x75/0xa9
[<c10903f9>] sys_read+0x3b/0x5d
[<c1002a8f>] sysenter_do_call+0x12/0x36
The fix is relatively simple, use the atomic variants of kmap() that
avoid the potential sleep.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Miles Lane <miles.lane@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Ironlake suspend/resume support
drm/i915: kill warning in intel_find_pll_g4x_dp
drm/i915: update watermarks before enabling PLLs
drm/i915: add FIFO watermark support for G4x
drm/i915: quiet DP i2c init
drm/i915: fix panel fitting filter coefficient select for Ironlake
drm/i915: fix to setup display reference clock control on Ironlake
drm/i915: Install a fence register for fbc on g4x
drm/i915: save/restore BLC histogram control reg across suspend/resume
drm/i915: Fix FDI M/N setting according with correct color depth
drm/i915: disable powersave feature for Ironlake currently
drm/i915: Fix render reclock availability detection.
drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
drm/i915: disable FBC for Pineview, fixing a boot hang.
Noticed by Andre on IRC.
Also fix up some minor whitespace issues.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The Lenovo W500 laptop hangs inside an SMI on brightness changes,
I thought it just needed the VGA disable but it turned out to require
slightly more work, setting the MC locations up just like the IGP
chip requirements seems to make it all happy again and I can boot
and play with brightness.
We should probably just do this for all chips and give up the VRAM
at 0x0 idea, it never seems to buy us anything but pain.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Once kms is enabled we don't need these, and it causes a problem
with the Lenovo W500 ACPI brightness implementation, it hangs
in a loop inside an SMI.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Immediate readback seems faulty on some chips. I
suspect it takes a while to get through the fifo
to the actual register backbone. There's no need
to read it back, so, just write the driver's copy
of the register's value directly.
Should fix bug 24535 and possibly 24218
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
When we are evicting from VRAM->RAM we allocate the ttm object,
but we don't set the caching policy on it before blitting into it.
This means on AGP we end up blitting into cached pages, and
the CPU later flushes out on top of them. This was mostly seen as
font corruption.
The other question is why we don't evict VRAM->GTT in a lot of cases,
this would save us some cache transitions since a lot of objects
that are evicted from VRAM will probably end up being pulled back in
a few operations later, and evicting them to system memory involves
2 unnecessary cache transitions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
In commit c1c7af6089 ("drm/i915: force
mode set at lid open time") the intel graphics driver was taught to
restore the LVDS mode on lid open.
That caused problems with interaction with the suspend/resume code,
which commonly runs at the same time (suspend is often caused by the lid
close event, while lid open is commonly a resume event), which was
worked around with in commit 06891e27a9
("drm/i915: fix suspend/resume breakage in lid notifier").
However, in the meantime the lid event code had also grown a user event
notifier (commit 06324194ee: "drm/i915:
generate a KMS uevent at lid open/close time"), and now _that_ causes
problems with suspend/resume and some versions of Xorg reacting to those
uevents by setting the mode.
So this effectively reverts that commit 06324194ee, and makes the lid
open protection logic against suspend/resume more explicit. This fixes
at least one laptop. See
http://bugzilla.kernel.org/show_bug.cgi?id=14484
for more details.
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This fixes suspend/resume on my rc410 motherboard, it restores
the memory controller setup before posting the GPU, since it seems
to need the MC_FB_LOCATION setup correctly.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Make sure we have an LVDS encoder before casting enc_priv.
[airlied: also fix two missing cpu_to_le16 casts we noticed on irc]
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Make the struct card_info, which is a per struct radeon_device dataset, a
struct member of the radeon device instead of a static per kernel module
value. This should avoid potential problems with two radeon cards installed in
one system.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
DVO in 12 bit mode (which seems to be the most common
config) requires 2x ppll.
Fixes fdo bug 21857.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Limiting the pll output range is a good thing generally as
it limits the number of possible pll combinations for a given
frequency presumably to the ones that work best on each card.
That's why the limits are in the bios tables. However, certain
duallink DVI monitors seem to like pll combinations that would
be limited by this at least on pre-DCE 3.0 r6xx hardware. This
might need to be adjusted per family or per clock range in the
future.
See fdo bug 24727.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
>hsync/vsync width is zero
>sync is beyond the blank.
So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Since we register all radeon devices, and the arbiter only cares about
VGA class ones, we will fail to startup on display controller class devices.
We don't gain anything by using the return value here.
this helps kms on sparc64 get started.
Reported-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Spread spectrum is a periodic disturbance added
to the feedback divider to change the pixel clock
periodically to reduce interference.
Only enabled on LVDS.
v2: add support for r4xx and fix DCE 3
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The *_HIGH regs are reversed. The secondary ones are in the
primary block and vice versa.
We currently only use a 32 bit internal address, so these are
0 for now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This patch only changes this is the swap path, where it doesn't loop.
Signed-off-by: Robert Noland <rnoland@2hip.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
- Reduce the chance of error and avoid a bit of overhead.
- Use switch to assign color and format
Signed-off-by: Robert Noland <rnoland@2hip.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Where supported use ulMinPixelClockPLL_Output rather than
usMinPixelClockPLL_Output for pll_out_min. This seems to
improve pll selection on some boards.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The problem boils down to the order when the bit11
of the texture size is or'ed to the original width.
In the end each mipmap level has the same width or
height because of that 11 bit is ored to the scaled
down lod with and thus blows up the size again to the
full size or more due to the power of two rounding
afterwards.
The attached patch changes this order so that the
texture sizes are computed correct. Also the on error
the yet missing inputs to the size computation are
printed which helped me to find out where it really breaks.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
This adds registers save/restore for Ironlake to make suspend work.
Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com>
[zhenyuw: some code re-orgnization, and add more save/restore for
FDI link and transcoder registers, also fix palette register for Ironlake]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
When coming back from DPMS or turning on a display, make sure we have
the watermarks set up before turning on the display plane, otherwise we
may get underruns.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Turns out G4x needs to have sensible watermarks set, especially for
self-refresh enabled modes. Add support for it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Must set filter selection as hardcoded coefficients for medium 3x3
filtering, which matches vbios setting for Ironlake.
This fixes display corrupt issue on HP arrandale with new vbios.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
For new stepping of PCH, the display reference clock
is fully under driver's control. This one trys to setup
all needed reference clock for different outputs. Older
stepping of PCH chipset should be ignoring this.
This fixes output failure issue on newer PCH which requires
driver to take control of reference clock enabling.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Original radeon didn't have a connector table in the
bios. Check for the CRT table and if we have one,
add a VGA connector.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Need to check the return type for the quirk function
to decide whether we add the connectors and encoders.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
>hsync/vsync width is zero
>sync is beyond the blank.
So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
D1MODE_INTERLEAVE_EN was getting set in some cases
in the encoder quirks function due to the changes in
5a9bcacc0a
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Based partly on a patch from
Christian Koenig <deathsimple@vodafone.de>
- fix several memory leaks in radeon_connector->edid handling
- store edid in radeon_connector->edid in detect() or get_modes()
- switch hdmi detect code to use radeon_connector->edid
- add support for oem boards multiple connectors that share
a ddc line.
- short circuit lvds_detect() if have a stored edid
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
To enable framebuffer compression on a g4x, we not only need the buffer
to tiled (X only), we also need to hold a fence register for the buffer.
Currently we only install a fence register for pre-i965s when setting up
the scanout buffer. Rather than adding some convoluted logic to
g4x_enable_fbc() to acquire a fence register, and perhaps to
g4x_disable_fbc() to release it again, we can extend the acquisition
during setup to all chipsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Turns out some machines, like the ThinkPad X40 don't come back if you
don't save/restore this register.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
- crtc 0 routing was wrong
- need to clear various timing bits in FP_GEN_CNTL
- need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
radeon_encoder->active_device defines the active routing
between the encoder and connector. The encoder fixup and
dpms functions need to know the active_device to function
properly. Setting active_device in the prepare hook was
too late in some cases.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
FDI M/N calculation hasn't taken the current pipe color depth into account,
but always set as 24bpp. This one checks current pipe color depth setting,
and change FDI M/N calculation a little to use bits_per_pixel first, then
convert to bytes_per_pixel later.
This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel
in 18bpp dual-channel mode.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Until we figure out the right setting for powersave features on
Ironlake, disable it for now. Also disable watermark update,
which has new registers for it on Ironlake too.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Resolved against the Pineview FBC changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
If the device didn't support EDP, we would bail out too soon.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Pulled this patch out of the patch for adding quirks to
enable reclocking.]
Signed-off-by: Eric Anholt <eric@anholt.net>
This hasn't fixed the regressions we were testing against, but clearly
should be required.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
According to the spec the LVDS_BORDER_ENABLE bit decides whether the border
data should be included in the active display and data sent to the panel.
Border should be used when in VGA centered (un-scaled) mode or when scaling
a 4:3 source image to a wide screen panel (typical 16:9).
So when the LVDS scaling is used, decide whether the LVDS_BORDER should be
enabled or not according to the current scaling mode.
At the same time fix the typo error in LVDS center scaling mode.
https://bugs.freedesktop.org/show_bug.cgi?id=23789
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
tested-by: Zhao Jian <jian.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Pineview doesn't have this FBC mechanism, so this code doesn't apply.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
drm modes are objects with indentifiers. Make sure to preserve
the mode id when copying mode params.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
In case the system has bad native mode info but
valid edid.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This reduces the number of mode format conversions needed
and makes native panel mode support cleaner.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
- clean up tv timing handling
- unify SetCRTC_Timing and SetCRTC_UsingDTDTiming
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
DCE3+ has an AdjustDisplayPll that will adjust the pixel
clock accordingly based on the encoder/transmitter to
handle special hw requirements.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
If the panel data is bogus this can lead to problems
later when the hardware trys to set the mode. If the
data is invalid, report LVDS as disconnected.
Should fix fdo bug 24247.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
While investigating the cause of CRTC FIFO underruns, I noticed that when
converting the memory bandwidth calculation from the userspace X driver code,
an instance of '8.0' was apparently accidentally converted to '80'.
Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The hook may change the number of bytes per pixel being scanned out, which
affects the CRTC memory bandwidth requirements. E.g. booting in 8bpp and then
running X in 32bpp would result in the bandwidth requirements being
underestimated for the latter and consequently in CRTC FIFO underruns causing
visible artifacts with 3D intensive workloads.
ATOM changes only compile-tested.
Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Initialize HDMI outputs as HDMI connectors, not DVI.
drm/i915: Multiply the refresh by 1000 in TV mode validatiion
drm/i915: Enable irq to trace batch buffer completion.
drm/i915: batch submit seqno off-by-one.
drm/i915: Record device minor rather than pointer in TRACE_EVENT
drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_set
conflict in radeon since new init path merged with vga arb code.
Conflicts:
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_device.c
There is no need to assign vb before you know that space is available.
[agd5f: adapted for kernel tree.]
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
For AGP to work unmapped access must cover VRAM & AGP as
AGP is treated like VRAM by the GPU (ie physical address).
This patch properly setup the virtual memory system aperture
to cover AGP if AGP is enabled. It seems that there is memory
corruption after resume when using AGP (RV770 seems unaffected
thought). Version 2 just fix merge issue with updated AGP
fallback patch.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
When GPU acceleration is not working with AGP try to fallback to non
AGP GART (either PCI or PCIE GART). This should make KMS failure on
AGP less painfull. We still need to find out what is wrong when AGP
fails but at least user have a lot of more chances to get a working
configuration with acceleration. This patch also cleanup R600/RV770
fallback path so they use same code as others asics. Version 2
factorize agp disabling logic to avoid code duplication and bugs.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bad generated header file leaded to use wrong register
to check IRQ status and acknowledge them. Fix the header
and use proper registers.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
the global refcount wasn't being increased after the first reference.
this caused an oops on unload on a multi-gpu card.
Signed-off-by: Dave Airlie <airlied@redhat.com>
The previous patches had some unwanted side effects, I've fixed
the lack of 32bpp working, and fixed up 16bpp so it should also work.
this also adds the interface to allow the driver to set a preferred
console depth so for example low memory rn50 can set it to 8bpp.
It also catches 24bpp on cards that can't do it and forces 32bpp.
Tested on r100/r600/i945.
Signed-off-by: Dave Airlie <airlied@redhat.com>
This adds support for the setcmap api and fixes the 8bpp
support at least on radeon hardware. It adds a new load_lut
hook which can be called once the color map is setup.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Also add single crtc for RN50 chips.
changes in v2:
fix vblank init to respect single crtc flag
fix r100 mode bandwidth to respect single crtc flag
Signed-off-by: Dave Airlie <airlied@redhat.com>
We can get the corresponding info by adding the boot option of "drm.debug=
0x07". But On some boxes it will print the following message many times in
course of moving mouse. In such case the useful DRM debug info will be flushed.
>[drm:drm_mode_cursor_ioctl],
Avoid using the DRM_DEBUG_KMS in drm_mode_cursor_ioctl.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
"Surround View" is an option in the system bios that
enables the AMD IGP chip in conjunction with a
discrete AMD card. However, since the IGP vbios is
part of the system bios it is not accessible via the
rom bar or the legacy vga location. When "Surround View"
is enabled in the system bios, the system bios puts a
copy of the IGP vbios image at the start of vram.
This patch adds support for reading the vbios image out
of vram on IGP cards.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Even if the physical output connector is DVI, calling it HDMI
tells the user that there's HDMI audio signaling support.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
