Update the mapping of the memory controler registers and
add the missing definitions of the register block for the
SSMC.
The register contents definitions can be found in the pl093
header.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Currently map-base.h defines the main virtual address mappings made
for all the support S3C SoC series, but does not then define any base
for per-cpu mappings to be made from.
Add S3C_ADDR_CPU() macro to define an virtual address as an offset
from the last of the core mappings.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add entries to select the crystal to select for each different
supported board. This information is then available for anything
else requiring this, such as the CPUFreq PLL tables.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add io-timing support for frequency scaling on the S3C2410 SoC.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add the S3C24XX to the main ARM CPUFreq Kconfig support list.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add ARCH_HAS_CPUFREQ so that each machine config can select
it if they have CPUFREQ driver support. This means that the
CPUFREQ specific area does not need the if statement updating
each time a new machine is added.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Move the structure s3c_cpufreq_config from cpu-freq.h to the
less advertised cpu-freq-core.h as it is not needed by anything
outside the core drivers.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Update arch/arm/plat-s3c/include/plat/cpu-freq.h to include kerneldoc
style documentation.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add the core of the support for enabling the CPUFreq driver on
all S3C24XX based systems.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add definitions and an accessor macro to deal with
reading bus information from S3C2410_BWSCON for any
given numbered bank.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The value of armclk_mask needs to be inverted for use as a mask on
the register value when updating ARM_RATIO.
This is critical for cpufreq support, without it attempts to scale
the frequency of the core trash pretty much the entire clock tree.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
If the requested clock is faster than the parent clock then the
parent clock is the closest we can get to the request so we need
to return that instead of the requested clock.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
In the s3c_gpiolib_getchip implementation for s3c24xx the check whether a pin is
in the gpio banks range is reversed. Thus the function returns NULL for valid
pins and the gpio chip if its not valid.
As a result gpio states are not saved/restored properly during suspend/resume.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* 'drm-radeon-kms' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (35 commits)
drm/radeon: set fb aperture sizes for framebuffer handoff.
drm/ttm: fix highuser vs dma32 confusion.
drm/radeon: Fix size used for benchmarking BO copies.
drm/radeon: Add radeon.test parameter for running BO GPU copy tests.
drm/radeon/kms: allow interruptible waits for objects.
drm/ttm: powerpc: Fix Highmem cache flushing.
x86: Export kmap_atomic_prot() needed for TTM.
drm/ttm: Fix ttm in-kernel copying of pages with non-standard caching attributes.
drm/ttm: Fix an oops and sync object leak.
drm/radeon/kms: vram sizing on certain r100 chips needs workaround.
drm/radeon: Pay more attention to object placement requested by userspace.
drm/radeon: Fall back to evicting BOs with memcpy if necessary.
drm/radeon: Don't unreserve twice on failure to validate.
drm/radeon/kms: fix bandwidth computation on avivo hardware
drm/radeon/kms: add initial colortiling support.
drm/radeon/kms: fix hotspot handling on pre-avivo chips
drm/radeon/kms: enable frac fb divs on rs600/rs690/rs740
drm/radeon/kms: add PLL flag to prefer frequencies <= the target freq
drm/radeon/kms: block RN50 from using 3D engine.
drm/radeon/kms: fix VRAM sizing like DDX does it.
...
This functionality is needed to kmap_atomic() highmem pages that may
potentially have or are about to set up other mappings with
non-standard caching attributes.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Those definitions are already provided by asm-generic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* 'fixes-for-linus' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Makefile cleanup
microblaze: Typo fix for cpu param inconsistency
microblaze: Add support for R_MICROBLAZE_64_NONE
microblaze: Get module loading working
microblaze: remove sys_ipc
microblaze: Support unaligned address for put/get_user macros
microblaze: Detect new Microblaze 7.20 versions
microblaze: Fix do_page_fault for no context
microblaze: Add _PAGE_FILE macros to pgtable.h
microblaze: Fix put_user macro for 64bits arguments
microblaze: Clear print messages for DTB passing via r7
microblaze: Not to clear r7 after copying DTB to kernel
microblaze: Add messages about FDT blob
microblaze: Final support for statically linked DTB
microblaze: remove duplicated #include
microblaze: Define tlb_flush macro
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86: geode: Mark mfgpt irq IRQF_TIMER to prevent resume failure
x86, amd: Don't probe for extended APIC ID if APICs are disabled
x86, mce: Rename incorrect macro name "CONFIG_X86_THRESHOLD"
x86-64: Fix bad_srat() to clear all state
x86, mce: Fix set_trigger() accessor
x86: Fix movq immediate operand constraints in uaccess.h
x86: Fix movq immediate operand constraints in uaccess_64.h
x86: Add reboot fixup for SBC-fitPC2
x86: Include all of .data.* sections in _edata on 64-bit
x86: Add quirk for Intel DG45ID board to avoid low memory corruption
* 'for-linus' of git://git390.marist.edu/pub/scm/linux-2.6:
[S390] zcrypt: fix scheduling of hrtimer ap_poll_timer
[S390] vdso: clock_gettime of CLOCK_THREAD_CPUTIME_ID with noexec=on
[S390] vdso: fix per cpu area allocation
[S390] hibernation: fix register corruption on machine checks
[S390] hibernation: fix lowcore handling
mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()
Upcoming paches to support the new 64-bit "BookE" powerpc architecture
will need to have the virtual address corresponding to PTE page when
freeing it, due to the way the HW table walker works.
Basically, the TLB can be loaded with "large" pages that cover the whole
virtual space (well, sort-of, half of it actually) represented by a PTE
page, and which contain an "indirect" bit indicating that this TLB entry
RPN points to an array of PTEs from which the TLB can then create direct
entries. Thus, in order to invalidate those when PTE pages are deleted,
we need the virtual address to pass to tlbilx or tlbivax instructions.
The old trick of sticking it somewhere in the PTE page struct page sucks
too much, the address is almost readily available in all call sites and
almost everybody implemets these as macros, so we may as well add the
argument everywhere. I added it to the pmd and pud variants for consistency.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV]
Acked-by: Nick Piggin <npiggin@suse.de>
Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Reviewed the Makefile on request by Michal and this is the resulting changes.
o Use ':=' for assignmnet so we do not re-evaluate for each use
o Use $(shell echo xxx) to remove ""
o Replaced CFLAGS_KERNEL with KBUILD_CFLAGS
The settings are equally relevant for modules and the linked kernel
o Dropped LDFLAGS_BLOB - it is no longer used
o Refactored assignmnets to libs-y and core-y
o Use MMU for the MMU specific extension. "MMUEXT" was hurting my eyes
and I did not wanted it spread to m68k
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Michal Simek <monstr@monstr.eu>
New reloc type R_MICROBLAZE_32_PCREL_LO requires a null handler (no work to do).
Remove legacy hack for broken linker pre gcc-4.1.1, that required us to extract
an offset from the code, add it to the addend, then rewrite the instruction.
Fixup the invalid reloc type error output.
Boot tested with the xilinx_emaclite ethernet driver.
Signed-off-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
The ipc system call is now unused in microblaze,
as the system call table points directly to the
indidual system calls for IPC.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch add support for cases where load/store instruction
in put/get_user macro gets unaligned pointer to data and this
address is not valid. I prevent all cases which can failed.
I had to disable first stage of unaligned handler which is used
only for noMMU kernel and the whole work is done when interrupt
is enabled.
You have enable HW support for detect unaligned access in Microblaze.
This patch fixed three LTP tests:
getpeername01, getsockname01, socketpair01
Signed-off-by: Michal Simek <monstr@monstr.eu>
Calling fixup when we are in kernel mode. This
prevent fault for copy_to/from_user. This fault
was find thanks to writev01/03/04 LTP tests.
Signed-off-by: Michal Simek <monstr@monstr.eu>
We need to define _PAGE_FILE macro and change pte
functions. Microblaze use the same MMU as PowerPC
that's why we define _PAGE_FILE in the same style.
This change fixed remap_file_pages01 LTP test.
Signed-off-by: Michal Simek <monstr@monstr.eu>
For 64bits arguments gcc caused that put_user macro
works with wrong value because of optimalization.
Adding volatile caused that gcc not optimized it.
It is possible to use (as Blackfin do) two put_user
macros with 32bits arguments but there is one more
instruction which is due to duplication zero return
value which is called put_user_asm macro.
Signed-off-by: Michal Simek <monstr@monstr.eu>
It is necessary to zeroed r7 when r7 points to bad
dtb - this caused that we have correct messages
about compiled-in dtb or passing via r7
Signed-off-by: Michal Simek <monstr@monstr.eu>
If r7 is zero at kernel boot, or does not point to a valid DTB, then
we fall back to a DTB (assumed to be) linked statically in the kernel, instead
of blindly copying bogus cruft into the kernel DTB memory region
Signed-off-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This fix remove bug which we had till now in all
Microblaze MMU code. Primary tested on mmap01 LTP test.
We forget to flush invalid tlb which were changed - we
used them and there were wrong old data which wasn't correct.
Signed-off-by: Michal Simek <monstr@monstr.eu>
The combination of noexec=on and a clock_gettime call with clock id
CLOCK_THREAD_CPUTIME_ID is broken. The vdso code switches to the
access register mode to get access to the per-cpu data structure to
execute the magic ectg instruction. After the ectg instruction the
code always switches back to the primary mode but for noexec=on the
correct mode is the secondary mode. The effect of the bug is that the
user space program looses the access to all mappings without PROT_EXEC,
e.g. the stack. The problem is fixed by restoring the mode that has
been active before the switch to the access register mode.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
vdso per cpu area allocation in smp_prepare_cpus() happens with GFP_KERNEL
but irqs disabled. Triggers this one:
Badness at kernel/lockdep.c:2280
Modules linked in:
CPU: 0 Not tainted 2.6.30 #2
Process swapper (pid: 1, task: 000000003fe88000, ksp: 000000003fe87eb8)
Krnl PSW : 0400c00180000000 0000000000083360 (lockdep_trace_alloc+0xec/0xf8)
[...]
Call Trace:
([<00000000000832b6>] lockdep_trace_alloc+0x42/0xf8)
[<00000000000b1880>] __alloc_pages_internal+0x3e8/0x5c4
[<00000000000b1b4a>] __get_free_pages+0x3a/0xb0
[<0000000000026546>] vdso_alloc_per_cpu+0x6a/0x18c
[<00000000005eff82>] smp_prepare_cpus+0x322/0x594
[<00000000005e8232>] kernel_init+0x76/0x398
[<000000000001bb1e>] kernel_thread_starter+0x6/0xc
[<000000000001bb18>] kernel_thread_starter+0x0/0xc
Fix this by moving the allocation out of the irqs disabled section.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
swsusp_arch_suspend() actually saves all cpu register contents on
hibernation.
Machine checks must be disabled since swsusp_arch_suspend() stores
register contents to their lowcore save areas. That's the same
place where register contents on machine checks would be saved.
To avoid register corruption disable machine checks.
We must also disable machine checks in the new psw mask for
program checks, since swsusp_arch_suspend() may generate program
checks.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Our swsusp_arch_suspend() backend implementation disables prefixing
by setting the contents of the prefix register to 0.
However afterwards common code functions are called which might
access percpu data structures.
Since the lowcore contains e.g. the percpu base pointer this isn't
a good idea. So fix this by copying the hibernating cpu's lowcore to
absolute address zero.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Timer interrupts are excluded from being disabled during suspend. The
clock events code manages the disabling of clock events on its own
because the timer interrupt needs to be functional before the resume
code reenables the device interrupts.
The mfgpt timer request its interrupt without setting the IRQF_TIMER
flag so suspend_device_irqs() disables it as well which results in a
fatal resume failure.
Adding IRQF_TIMER to the interupt flags when requesting the mrgpt
timer interrupt solves the problem.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
LKML-Reference: <new-submission>
Cc: Andres Salomon <dilinger@debian.org>
Cc: stable@kernel.org
* 'perf-counters-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/peterz/linux-2.6-perf: (31 commits)
perf_counter tools: Give perf top inherit option
perf_counter tools: Fix vmlinux symbol generation breakage
perf_counter: Detect debugfs location
perf_counter: Add tracepoint support to perf list, perf stat
perf symbol: C++ demangling
perf: avoid structure size confusion by using a fixed size
perf_counter: Fix throttle/unthrottle event logging
perf_counter: Improve perf stat and perf record option parsing
perf_counter: PERF_SAMPLE_ID and inherited counters
perf_counter: Plug more stack leaks
perf: Fix stack data leak
perf_counter: Remove unused variables
perf_counter: Make call graph option consistent
perf_counter: Add perf record option to log addresses
perf_counter: Log vfork as a fork event
perf_counter: Synthesize VDSO mmap event
perf_counter: Make sure we dont leak kernel memory to userspace
perf_counter tools: Fix index boundary check
perf_counter: Fix the tracepoint channel to perfcounters
perf_counter, x86: Extend perf_counter Pentium M support
...
If we've logically disabled apics, don't probe the PCI space for the
AMD extended APIC ID.
[ Impact: prevent boot crash under Xen. ]
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Reported-by: Bastian Blank <bastian@waldi.eu.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Ben Dooks