There are no current users and new drivers ought to be using the regmap
API and its cache implementation directly so just delete the ASoC copy.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
These aren't modules, but they do make use of these macros, so
they will need export.h to get that definition. Previously,
they got it via the implicit module.h inclusion.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Currently the condition for these WARN_ONs is reversed and they are placed
before the actual check whether we are going to write to that register. So if
the codec implements the register_writable callback we'll get a warning for each
writable register when syncing the register cache.
While we are at it change the check to use snd_soc_codec_writable_register
instead of open-coding it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Since commit aea170a099
"ASoC: soc-cache: Add reg_size as a member to snd_soc_codec",
the codec_drv pointer variable is not used in snd_soc_lzo_get_blksize.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Since commit d779fce5d7
"ASoC: soc-cache: Ensure flat compression uses a copy of the defaults cache",
the codec_drv pointer variable is not used any more.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For clarity and to help ongoing refactoring in this area create a new file
to contain the physical I/O functions, separating them out from the cache
operations.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
We've got a whole bunch of functions which just call straight through to
do_hw_read(). Simplify this situation by removing them and using hw_read()
directly.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Currently the rbtree code will write out the entire register map when
doing a cache sync which is wasteful and will slow things down. Check
to see if the value we're about to write is the default and don't bother
restoring it if it is, either the value will have been retained or the
device will have been reset and holds the value already.
We should really store the defaults in the nodes but this resolves the
immediate issue.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Run the data through cpu_to_be16() so it's at least clear what we're up to.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Whenever we are doing a read or a write through the rbtree code, we'll
cache a pointer to the rbnode. To avoid looking up the register
everytime we do a read or a write, we first check if it can be found in
the cached register block, otherwise we traverse the rbtree and finally
cache the rbnode for future use.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch prepares the ground for the actual rbtree optimization patch
which will save a pointer to the last accessed rbnode that was used
in either the read() or write() functions.
Each rbnode manages a variable length block of registers. There can be no
two nodes with overlapping blocks. Each block has a base register and a
currently top register, all the other registers, if any, lie in between these
two and in ascending order.
The reasoning behind the construction of this rbtree is simple. In the
snd_soc_rbtree_cache_init() function, we iterate over the register defaults
provided by the driver. For each register value that is non-zero we
insert it in the rbtree. In order to determine in which rbnode we need
to add the register, we first look if there is another register already
added that is adjacent to the one we are about to add. If that is the case
we append it in that rbnode block, otherwise we create a new rbnode
with a single register in its block and add it to the tree.
In the next patch, where a cached rbnode is used by both the write() and the
read() functions, we also check if the register we are about to add is in the
cached rbnode (the least recently accessed one) and if so we append it in that
rbnode block.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
There is an unfortunate difference in return values between spi_write()
and i2c_master_send() so we need an adaptor function to translate.
Reported-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
do_spi_write() is just an open coded copy of do_spi_write() so we can
delete it and just call spi_write() directly. Indeed, as a result of
recent refactoring all the SPI write functions are just very long
wrappers around spi_write() which don't add anything except for some
pointless copies so we can just use spi_write() as the hw_write
operation directly. It should be as type safe to do this as it is to do
the same thing with I2C and it saves us a bunch of code.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
snd_soc_4_12_spi_write() contains a byte swap. Since this code was written
for an Analog CODEC on a Blackfin reference board it appears that this is
done because while Blackfin is little endian the CODEC is big endian (as
are most CODECs).
Push this up into the generic 4x12 write function and use cpu_to_be16() to
do the byte swap so things are more regular and things work on both CPU
endiannesses.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Currently we'll force all registers to fit in 8 bits before passing
down to the I/O function. Looks like a cut'n'paste bug.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
If we specifically want to write a block of data to the hw bypassing the
cache, then allow this to happen inside snd_soc_hw_bulk_write_raw().
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
`type` parameter is not longer used in `snd_soc_codec_set_cache_io`,
so remove this line.
Signed-off-by: Lu Guanqun <guanqun.lu@intel.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch fixes to avoid compile error when ASoC codec doesn't use I2C
nor SPI on snd_soc_hw_bulk_write_raw().
Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
When syncing the cache, if the driver has given us a writable_register()
callback, use it to check if we are syncing a non-writable register
and if so warn the user.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
By using struct snd_soc_reg_access for the read/write/vol attributes
of the registers, we provide callbacks that automatically determine whether
a given register is readable/writable or volatile.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
These functions fail with -EINVAL if the corresponding callbacks
are not implemented. Change them to return -ENOSYS as it is more
appropriate for unimplemented callbacks.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The handling of all snd_soc_x_y_spi_write() functions is similar.
Create a separate function and update all callers to use it.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The handling of all snd_soc_x_y_read() functions is similar.
Factor it out into a separate function and update all callers.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The handling of all snd_soc_x_y_write() functions is similar.
Factor it out into a separate function and update all functions
to use it.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
As it has become more common to have to write firmware or similar
large chunks of data to the hardware, add a function to perform
raw bulk writes that bypass the cache. This only handles volatile
registers as we should avoid getting out of sync with the actual
cache.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The handling of all snd_soc_x_y_read_i2c() functions is similar.
Make a generic I2C read function and update all callers to use it.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The patch c358e640a6 "ASoC: soc-cache: Add trace event for
snd_soc_cache_sync()" introduced a dereference of "codec->cache_ops"
before we had checked it for NULL.
I pulled the check forward, and then pulled everything in an indent
level.
Signed-off-by: Dan Carpenter <error27@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch makes it easy to see when the syncing process begins and
ends. You can also enable the snd_soc_reg_write tracepoint to see
which registers are being synced.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Incorporate the use of the cache_bypass functionality in the
syncing functions. The snd_soc_flat_cache_sync() need not be
hooked as there is no performance benefit from using the
cache_bypass option.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This is primarily needed to avoid writing back to the cache
whenever we are syncing the cache with the hardware. This gives a
performance benefit especially for large register maps.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For common scenarios, device drivers can provide a table of all the
registers that are at least either readable/writable/volatile. The idea
is that if a register lookup fails, all of its read/write/vol members
will be zero and will be treated as default. This also reduces the
size of the register access array.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Simplify the use of reg_size, by calculating it once and storing it in
the codec structure for later reference. The value of reg_size is
reg_cache_size * reg_word_size.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
With the addition of the cache fallback functionality, it is necessary
to ensure that if the register defaults cache was marked as __devinitconst
and the LZO compression is not compiled in the kernel, the fallback to
flat compression will still use a copy of the defaults cache.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Use Takashi's clean up code to make the cache manipulation code more
readable.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The size of the lzo syncing bitmap was incorrectly set to the size
of the cache times the word size, however, the correct size is the
size of the cache.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Make LZO cache compression optional as it pulls in the kernel wide LZO
implementation and rbtree compression is generally more efficient for
typical register maps, especially in terms of CPU performance.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
This makes it easier to make cache types build time configurable as we
don't have a hard dependency on a given cache being built in.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Remove redundant parentheses/spaces in the use of the sizeof
operator.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mark Brown