Newer firmware can post CPL_SGE_EGR_UPDATE message encapsulated in a
CPL_FW4_MSG as follows
flit0 rss_header (if DropRSS == 0 in IQ context)
flit1 CPL_FW4_MSG cpl
flit2 rss_header w/opcode CPL_SGE_EGR_UPDATE
flit3 CPL_SGE_EGR_UPDATE cpl
So FW4_MSG CPLs with a newly created type of FW_TYPE_RSSCPL have the
CPL_SGE_EGR_UPDATE CPL message in flit 2 of the FW4_MSG. Firmware can still
post regular CPL_SGE_EGR_UPDATE messages, so the drivers need to handle
both.
This patch also writes a new parameter to firmware requesting encapsulated
EGR_UPDATE. This allows firmware with this support to not break older drivers.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Newer firmware can post CPL_SGE_EGR_UPDATE message encapsulated in a
CPL_FW4_MSG as follows
flit0 rss_header (if DropRSS == 0 in IQ context)
flit1 CPL_FW4_MSG cpl
flit2 rss_header w/opcode CPL_SGE_EGR_UPDATE
flit3 CPL_SGE_EGR_UPDATE cpl
So FW4_MSG CPLs with a newly created type of FW_TYPE_RSSCPL have the
CPL_SGE_EGR_UPDATE CPL message in flit 2 of the FW4_MSG. Firmware can still
post regular CPL_SGE_EGR_UPDATE messages, so the drivers need to handle
both.
This patch also writes a new parameter to firmware requesting encapsulated
EGR_UPDATE. This allows firmware with this support to not break older drivers.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
It enables direct DMA by HW to memory region PBL arrays and fast register PBL
arrays from host memory, vs the T4 way of passing these arrays in the WR itself.
The result is lower latency for memory registration, and larger PBL array
support for fast register operations.
This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of
ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Santosh Rastapur <santosh@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
It establishes passive open connection through firmware work request. Passive
open connection will go through this path as now instead of listening server we
create a server filter which will redirect the incoming SYN packet to the
offload queue. After this driver tries to establish the connection using
firmware work request.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
It enables establishing active open connection using fw_ofld_connection work
request when cpl_act_open_rpl says TCAM full error which may be because
of LE hash collision. Current support is only for IPv4 active open connections.
Sets ntuple bits in active open requests. For T4 firmware greater than 1.4.10.0
ntuple bits are required to be set.
Adds nocong and enable_ecn module parameter options.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
[ Move all FW return values to t4fw_api.h. - Roland ]
Signed-off-by: Roland Dreier <roland@purestorage.com>
The T4 architecture is capable of filtering ingress packets at line rate
using the rule in TCAM. If packet hits a rule in the TCAM then it can be either
dropped or passed to the receive queues based on a rule settings.
This patch adds framework for managing filters and to use T4's filter
capabilities. It constructs a Firmware Filter Work Request which writes the
filter at a specified index to get the work done. It hosts shadow copy of
ingress filter entry to check field size limitations and save memory in the
case where the filter table is large.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
This patch contains updates to firmware/hardware header files shared
between csiostor and cxgb4/cxgb4vf, and the resulting changes to the
cxgb4/cxgb4vf source files.
Signed-off-by: Naresh Kumar Inna <naresh@chelsio.com>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Moves the drivers for the Chelsio chipsets into
drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile
changes.
CC: Divy Le Ray <divy@chelsio.com>
CC: Dimitris Michailidis <dm@chelsio.com>
CC: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Vipul Pandya