Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Hein Tibosch <hein_tibosch@yahoo.es>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, who uses this core on the
Zynq SoCs, opted for on.
Force it to off. This shouldn't change the behaviour for current users of the
macb, but enables usage on Zynq devices.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add information to the DMA Configuration Register to
maximize system performance:
- rx/tx packet buffer full memory size
- allow possibility to use INCR16 if supported
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Joachim Eastwood <manabian@gmail.com
Signed-off-by: David S. Miller <davem@davemloft.net>
Only the first register set is used for matching but
we support getting the initial hw addr from any of
the registers.
To prevent stale entries and false matches clear unused
register sets. This most important for the at91_ether
driver where u-boot always uses the 2nd register set.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
No longer used after gpio phy interrupt support was
removed from at91_ether.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Handle all TX errors, not only underruns. TX error management is
deferred to a dedicated workqueue.
Reinitialize the TX ring after treating all remaining frames, and
restart the controller when everything has been cleaned up properly.
Napi is not stopped during this task as the driver only handles
napi for RX for now.
With this sequence, we do not need a special check during the xmit
method as the packets will be caught by TX disable during workqueue
execution.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add macb_get_regs() ethtool function and its helper function:
macb_get_regs_len().
The version field is deduced from the IP revision which gives the
"MACB or GEM" information. An additional version field is reserved.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Ben Hutchings <bhutchings@solarflare.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Instead of masking head and tail every time we increment them, just let them
wrap through UINT_MAX and mask them when subscripting. Add simple accessor
functions to do the subscripting properly to minimize the chances of messing
this up.
This makes the code slightly smaller, and hopefully faster as well. Also,
doing the ring buffer management this way will simplify things a lot when
making the ring sizes configurable in the future.
Available number of descriptors in ring buffer function by David Laight.
Signed-off-by: Havard Skinnemoen <havard@skinnemoen.net>
[nicolas.ferre@atmel.com: split patch in topics, adapt to newer kernel]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add Gigabit Ethernet mode to GEM cadence IP and enable RGMII connection.
Signed-off-by: Patrice Vilchez <patrice.vilchez@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch does two things:
* Use macb struct members and remove at91_ether ones
* Alloc DMA buffers on netdev start and dealloc on stop
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
This rips out the at91_ether phy handling and ethtool stuff
and replace it with equivalent stuff from macb.
The only thing lost is the phy irq support from at91_ether,
but this can be added to macb and then benefit all users.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
This will make it easier to share code between the drivers and
eventually merge them into one driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Allow the device tree to provide the mac address and the phy mode.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre@atmel.com: change "compatible" node property, doc and DT hwaddr]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[jamie@jamieiles.com: add "gem" compatibility strings and doc]
Acked-by: Jamie Iles<jamie@jamieiles.com>
Acked-by: David S. Miller <davem@davemloft.net>
GEM has configurable receive buffer sizes so requires this to be
programmed up. Any size < 2048 and a multiple of 64 bytes is permitted.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Some GEM implementations may support DMA bus widths up to 128 bits. We
can get the maximum supported DMA bus width from the design
configuration register so use that to program the device up.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
GEM devices have a different number of statistics registers and they
are at a different offset to MACB devices. Make the statistics
collection method dependent on device type.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on the
device type.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The Cadence GEM is based on the MACB Ethernet controller but has a few
small changes with regards to register and bitfield placement. This
patch detects the presence of a GEM by reading the module ID register
and setting a flag appropriately.
This handles the new HW address, USRIO and hash register base register
locations in GEM.
v3: - convert to macb_is_gem() inline rather than storing a boolean
flag
- handle rx_overrun stats for gem
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Move the Atmel driver into drivers/net/ethernet/cadence/ and
make the necessary Kconfig and Makefile changes.
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre