2011-01-07 02:19:31 +00:00
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef NI_H
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#define NI_H
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2011-03-03 01:07:29 +00:00
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#define CAYMAN_MAX_SH_GPRS 256
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#define CAYMAN_MAX_TEMP_GPRS 16
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#define CAYMAN_MAX_SH_THREADS 256
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#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
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#define CAYMAN_MAX_FRC_EOV_CNT 16384
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#define CAYMAN_MAX_BACKENDS 8
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#define CAYMAN_MAX_BACKENDS_MASK 0xFF
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#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
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#define CAYMAN_MAX_SIMDS 16
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#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
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#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
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#define CAYMAN_MAX_PIPES 8
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#define CAYMAN_MAX_PIPES_MASK 0xFF
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#define CAYMAN_MAX_LDS_NUM 0xFFFF
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#define CAYMAN_MAX_TCC 16
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#define CAYMAN_MAX_TCC_MASK 0xFF
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#define DMIF_ADDR_CONFIG 0xBD4
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x00003000
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#define MC_SHARED_CHREMAP 0x2008
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2011-01-07 02:19:31 +00:00
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#define MC_SHARED_BLACKOUT_CNTL 0x20ac
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2011-03-03 01:07:29 +00:00
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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#define NOOFRANK_SHIFT 2
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#define NOOFRANK_MASK 0x00000004
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#define NOOFROWS_SHIFT 3
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#define NOOFROWS_MASK 0x00000038
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#define NOOFCOLS_SHIFT 6
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#define NOOFCOLS_MASK 0x000000C0
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#define CHANSIZE_SHIFT 8
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#define CHANSIZE_MASK 0x00000100
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#define BURSTLENGTH_SHIFT 9
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#define BURSTLENGTH_MASK 0x00000200
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#define CHANSIZE_OVERRIDE (1 << 11)
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2011-01-07 02:19:31 +00:00
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#define MC_SEQ_SUP_CNTL 0x28c8
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#define RUN_MASK (1 << 0)
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#define MC_SEQ_SUP_PGM 0x28cc
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#define MC_IO_PAD_CNTL_D0 0x29d0
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#define MEM_FALL_OUT_CMD (1 << 8)
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#define MC_SEQ_MISC0 0x2a00
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#define MC_SEQ_MISC0_GDDR5_SHIFT 28
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#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
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#define MC_SEQ_MISC0_GDDR5_VALUE 5
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#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
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#define MC_SEQ_IO_DEBUG_DATA 0x2a48
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2011-03-03 01:07:29 +00:00
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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#define HDP_NONSURFACE_INFO 0x2C08
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#define HDP_NONSURFACE_SIZE 0x2C0C
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#define HDP_ADDR_CONFIG 0x2F48
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#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
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#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
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#define CGTS_SYS_TCC_DISABLE 0x3F90
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#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
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#define CONFIG_MEMSIZE 0x5428
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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define GRBM_STATUS 0x8010
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#define CMDFIFO_AVAIL_MASK 0x0000000F
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#define RING2_RQ_PENDING (1 << 4)
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#define SRBM_RQ_PENDING (1 << 5)
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#define RING1_RQ_PENDING (1 << 6)
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#define CF_RQ_PENDING (1 << 7)
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#define PF_RQ_PENDING (1 << 8)
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#define GDS_DMA_RQ_PENDING (1 << 9)
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#define GRBM_EE_BUSY (1 << 10)
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#define SX_CLEAN (1 << 11)
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#define DB_CLEAN (1 << 12)
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#define CB_CLEAN (1 << 13)
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#define TA_BUSY (1 << 14)
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#define GDS_BUSY (1 << 15)
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#define VGT_BUSY_NO_DMA (1 << 16)
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#define VGT_BUSY (1 << 17)
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#define IA_BUSY_NO_DMA (1 << 18)
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#define IA_BUSY (1 << 19)
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#define SX_BUSY (1 << 20)
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#define SH_BUSY (1 << 21)
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#define SPI_BUSY (1 << 22)
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#define SC_BUSY (1 << 24)
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#define PA_BUSY (1 << 25)
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#define DB_BUSY (1 << 26)
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#define CP_COHERENCY_BUSY (1 << 28)
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#define CP_BUSY (1 << 29)
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#define CB_BUSY (1 << 30)
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#define GUI_ACTIVE (1 << 31)
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#define GRBM_STATUS_SE0 0x8014
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#define GRBM_STATUS_SE1 0x8018
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#define SE_SX_CLEAN (1 << 0)
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#define SE_DB_CLEAN (1 << 1)
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#define SE_CB_CLEAN (1 << 2)
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#define SE_VGT_BUSY (1 << 23)
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#define SE_PA_BUSY (1 << 24)
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#define SE_TA_BUSY (1 << 25)
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#define SE_SX_BUSY (1 << 26)
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#define SE_SPI_BUSY (1 << 27)
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#define SE_SH_BUSY (1 << 28)
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#define SE_SC_BUSY (1 << 29)
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#define SE_DB_BUSY (1 << 30)
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#define SE_CB_BUSY (1 << 31)
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#define GRBM_SOFT_RESET 0x8020
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#define SOFT_RESET_CP (1 << 0)
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#define SOFT_RESET_CB (1 << 1)
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#define SOFT_RESET_DB (1 << 3)
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#define SOFT_RESET_GDS (1 << 4)
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#define SOFT_RESET_PA (1 << 5)
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#define SOFT_RESET_SC (1 << 6)
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#define SOFT_RESET_SPI (1 << 8)
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#define SOFT_RESET_SH (1 << 9)
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#define SOFT_RESET_SX (1 << 10)
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#define SOFT_RESET_TC (1 << 11)
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#define SOFT_RESET_TA (1 << 12)
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#define SOFT_RESET_VGT (1 << 14)
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#define SOFT_RESET_IA (1 << 15)
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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#define CP_PERFMON_CNTL 0x87FC
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x) << 0)
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#define VC_ONLY 0
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#define TC_ONLY 1
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#define VC_AND_TC 2
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#define AUTO_INVLD_EN(x) ((x) << 6)
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#define NO_AUTO 0
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#define ES_AUTO 1
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#define GS_AUTO 2
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#define ES_AND_GS_AUTO 3
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#define VGT_GS_VERTEX_REUSE 0x88D4
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#define CC_GC_SHADER_PIPE_CONFIG 0x8950
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#define GC_USER_SHADER_PIPE_CONFIG 0x8954
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#define INACTIVE_QD_PIPES(x) ((x) << 8)
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#define INACTIVE_QD_PIPES_MASK 0x0000FF00
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#define INACTIVE_QD_PIPES_SHIFT 8
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#define INACTIVE_SIMDS(x) ((x) << 16)
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#define INACTIVE_SIMDS_MASK 0xFFFF0000
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#define INACTIVE_SIMDS_SHIFT 16
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#define VGT_PRIMITIVE_TYPE 0x8958
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#define VGT_NUM_INSTANCES 0x8974
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#define VGT_TF_RING_SIZE 0x8988
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#define VGT_OFFCHIP_LDS_BASE 0x89b4
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#define PA_SC_LINE_STIPPLE_STATE 0x8B10
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#define PA_CL_ENHANCE 0x8A14
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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#define PA_SC_FIFO_SIZE 0x8BCC
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#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
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#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
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#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
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#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
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#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
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#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
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#define SQ_CONFIG 0x8C00
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#define VC_ENABLE (1 << 0)
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#define EXPORT_SRC_C (1 << 1)
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#define GFX_PRIO(x) ((x) << 2)
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#define CS1_PRIO(x) ((x) << 4)
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#define CS2_PRIO(x) ((x) << 6)
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#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
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#define NUM_PS_GPRS(x) ((x) << 0)
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#define NUM_VS_GPRS(x) ((x) << 16)
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#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
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#define SQ_ESGS_RING_SIZE 0x8c44
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#define SQ_GSVS_RING_SIZE 0x8c4c
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#define SQ_ESTMP_RING_BASE 0x8c50
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#define SQ_ESTMP_RING_SIZE 0x8c54
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#define SQ_GSTMP_RING_BASE 0x8c58
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#define SQ_GSTMP_RING_SIZE 0x8c5c
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#define SQ_VSTMP_RING_BASE 0x8c60
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#define SQ_VSTMP_RING_SIZE 0x8c64
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#define SQ_PSTMP_RING_BASE 0x8c68
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#define SQ_PSTMP_RING_SIZE 0x8c6c
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#define SQ_MS_FIFO_SIZES 0x8CF0
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#define CACHE_FIFO_SIZE(x) ((x) << 0)
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#define FETCH_FIFO_HIWATER(x) ((x) << 8)
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#define DONE_FIFO_HIWATER(x) ((x) << 16)
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#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
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#define SQ_LSTMP_RING_BASE 0x8e10
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#define SQ_LSTMP_RING_SIZE 0x8e14
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#define SQ_HSTMP_RING_BASE 0x8e18
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#define SQ_HSTMP_RING_SIZE 0x8e1c
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#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
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#define DYN_GPR_ENABLE (1 << 8)
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#define SQ_CONST_MEM_BASE 0x8df8
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#define SX_EXPORT_BUFFER_SIZES 0x900C
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#define COLOR_BUFFER_SIZE(x) ((x) << 0)
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#define POSITION_BUFFER_SIZE(x) ((x) << 8)
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#define SMX_BUFFER_SIZE(x) ((x) << 16)
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#define SX_DEBUG_1 0x9058
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#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
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#define SPI_CONFIG_CNTL 0x9100
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#define GPR_WRITE_PRIORITY(x) ((x) << 0)
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#define SPI_CONFIG_CNTL_1 0x913C
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#define VTX_DONE_DELAY(x) ((x) << 0)
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#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
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#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
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#define CGTS_TCC_DISABLE 0x9148
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#define CGTS_USER_TCC_DISABLE 0x914C
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#define TCC_DISABLE_MASK 0xFFFF0000
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#define TCC_DISABLE_SHIFT 16
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#define CGTS_SM_CTRL_REG 0x915C
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#define OVERRIDE (1 << 21)
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#define TA_CNTL_AUX 0x9508
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#define DISABLE_CUBE_WRAP (1 << 0)
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#define DISABLE_CUBE_ANISO (1 << 1)
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#define TCP_CHAN_STEER_LO 0x960c
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#define TCP_CHAN_STEER_HI 0x9610
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define GB_ADDR_CONFIG 0x98F8
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#define NUM_PIPES(x) ((x) << 0)
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#define NUM_PIPES_MASK 0x00000007
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#define NUM_PIPES_SHIFT 0
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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
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#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
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#define PIPE_INTERLEAVE_SIZE_SHIFT 4
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#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
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#define NUM_SHADER_ENGINES(x) ((x) << 12)
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#define NUM_SHADER_ENGINES_MASK 0x00003000
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#define NUM_SHADER_ENGINES_SHIFT 12
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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
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#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
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#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
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#define NUM_GPUS(x) ((x) << 20)
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#define NUM_GPUS_MASK 0x00700000
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#define NUM_GPUS_SHIFT 20
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#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
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#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
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#define MULTI_GPU_TILE_SIZE_SHIFT 24
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#define ROW_SIZE(x) ((x) << 28)
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#define ROW_SIZE_MASK 0x30000007
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#define ROW_SIZE_SHIFT 28
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#define NUM_LOWER_PIPES(x) ((x) << 30)
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#define NUM_LOWER_PIPES_MASK 0x40000000
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#define NUM_LOWER_PIPES_SHIFT 30
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#define GB_BACKEND_MAP 0x98FC
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#define CB_PERF_CTR0_SEL_0 0x9A20
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#define CB_PERF_CTR0_SEL_1 0x9A24
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#define CB_PERF_CTR1_SEL_0 0x9A28
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#define CB_PERF_CTR1_SEL_1 0x9A2C
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#define CB_PERF_CTR2_SEL_0 0x9A30
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#define CB_PERF_CTR2_SEL_1 0x9A34
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#define CB_PERF_CTR3_SEL_0 0x9A38
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#define CB_PERF_CTR3_SEL_1 0x9A3C
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#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
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#define BACKEND_DISABLE_MASK 0x00FF0000
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#define BACKEND_DISABLE_SHIFT 16
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#define SMX_DC_CTL0 0xA020
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#define USE_HASH_FUNCTION (1 << 0)
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#define NUMBER_OF_SETS(x) ((x) << 1)
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#define FLUSH_ALL_ON_EVENT (1 << 10)
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#define STALL_ON_EVENT (1 << 11)
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#define SMX_EVENT_CTL 0xA02C
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#define ES_FLUSH_CTL(x) ((x) << 0)
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#define GS_FLUSH_CTL(x) ((x) << 3)
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#define ACK_FLUSH_CTL(x) ((x) << 6)
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#define SYNC_FLUSH_CTL (1 << 8)
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2011-01-07 02:19:31 +00:00
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#endif
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