2006-03-24 11:18:17 +00:00
|
|
|
/*
|
2007-07-11 18:04:50 +00:00
|
|
|
* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
|
2006-03-24 11:18:17 +00:00
|
|
|
*
|
mmc: sdhci: split up sdhci.h for sdhci-pltfm users
Some platforms based on sdhci-pltfm need to set their own quirks.
Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h.
This patch splits drivers/mmc/host/sdhci.h into two parts:
* drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors.
* include/linux/mmc/sdhci.h includes the sdhci structure and quirks.
Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should
now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h.
This patch avoids adding/changing the calls/flags in the
sdhci_pltfm_data structure. It has been tested on STM platforms
(e.g. STx7106, STx7108, STx5206) where the driver is configured
and used as shown in the example below:
[snip]
static int mmc_pad_resources(struct sdhci_host *sdhci)
{
if (!devm_stm_pad_claim(sdhci->mmc->parent,
&stx7108_mmc_pad_config,
dev_name(sdhci->mmc->parent)))
return -ENODEV;
return 0;
}
static struct sdhci_pltfm_data stx7108_mmc_platform_data = {
.init = mmc_pad_resources,
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
};
static struct platform_device stx7108_mmc_device = {
.name = "sdhci",
[snip]
Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h,
and no modifications should be needed on other sdhci-<XXX> drivers.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
2010-09-28 08:41:29 +00:00
|
|
|
* Header file for Host Controller registers and I/O accessors.
|
|
|
|
|
*
|
2008-03-08 22:44:25 +00:00
|
|
|
* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
|
2006-03-24 11:18:17 +00:00
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
2006-10-01 06:27:52 +00:00
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or (at
|
|
|
|
|
* your option) any later version.
|
2006-03-24 11:18:17 +00:00
|
|
|
*/
|
mmc: sdhci: split up sdhci.h for sdhci-pltfm users
Some platforms based on sdhci-pltfm need to set their own quirks.
Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h.
This patch splits drivers/mmc/host/sdhci.h into two parts:
* drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors.
* include/linux/mmc/sdhci.h includes the sdhci structure and quirks.
Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should
now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h.
This patch avoids adding/changing the calls/flags in the
sdhci_pltfm_data structure. It has been tested on STM platforms
(e.g. STx7106, STx7108, STx5206) where the driver is configured
and used as shown in the example below:
[snip]
static int mmc_pad_resources(struct sdhci_host *sdhci)
{
if (!devm_stm_pad_claim(sdhci->mmc->parent,
&stx7108_mmc_pad_config,
dev_name(sdhci->mmc->parent)))
return -ENODEV;
return 0;
}
static struct sdhci_pltfm_data stx7108_mmc_platform_data = {
.init = mmc_pad_resources,
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
};
static struct platform_device stx7108_mmc_device = {
.name = "sdhci",
[snip]
Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h,
and no modifications should be needed on other sdhci-<XXX> drivers.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
2010-09-28 08:41:29 +00:00
|
|
|
#ifndef __SDHCI_HW_H
|
|
|
|
|
#define __SDHCI_HW_H
|
2006-03-24 11:18:17 +00:00
|
|
|
|
2008-07-26 02:44:35 +00:00
|
|
|
#include <linux/scatterlist.h>
|
2009-03-16 21:13:46 +00:00
|
|
|
#include <linux/compiler.h>
|
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
#include <linux/io.h>
|
2008-07-26 02:44:35 +00:00
|
|
|
|
mmc: sdhci: split up sdhci.h for sdhci-pltfm users
Some platforms based on sdhci-pltfm need to set their own quirks.
Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h.
This patch splits drivers/mmc/host/sdhci.h into two parts:
* drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors.
* include/linux/mmc/sdhci.h includes the sdhci structure and quirks.
Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should
now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h.
This patch avoids adding/changing the calls/flags in the
sdhci_pltfm_data structure. It has been tested on STM platforms
(e.g. STx7106, STx7108, STx5206) where the driver is configured
and used as shown in the example below:
[snip]
static int mmc_pad_resources(struct sdhci_host *sdhci)
{
if (!devm_stm_pad_claim(sdhci->mmc->parent,
&stx7108_mmc_pad_config,
dev_name(sdhci->mmc->parent)))
return -ENODEV;
return 0;
}
static struct sdhci_pltfm_data stx7108_mmc_platform_data = {
.init = mmc_pad_resources,
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
};
static struct platform_device stx7108_mmc_device = {
.name = "sdhci",
[snip]
Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h,
and no modifications should be needed on other sdhci-<XXX> drivers.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
2010-09-28 08:41:29 +00:00
|
|
|
#include <linux/mmc/sdhci.h>
|
|
|
|
|
|
2006-03-24 11:18:17 +00:00
|
|
|
/*
|
|
|
|
|
* Controller registers
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define SDHCI_DMA_ADDRESS 0x00
|
2011-05-23 20:06:39 +00:00
|
|
|
#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_BLOCK_SIZE 0x04
|
2006-07-02 15:51:35 +00:00
|
|
|
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_BLOCK_COUNT 0x06
|
|
|
|
|
|
|
|
|
|
#define SDHCI_ARGUMENT 0x08
|
|
|
|
|
|
|
|
|
|
#define SDHCI_TRANSFER_MODE 0x0C
|
|
|
|
|
#define SDHCI_TRNS_DMA 0x01
|
|
|
|
|
#define SDHCI_TRNS_BLK_CNT_EN 0x02
|
2011-05-23 20:06:37 +00:00
|
|
|
#define SDHCI_TRNS_AUTO_CMD12 0x04
|
2011-05-23 20:06:39 +00:00
|
|
|
#define SDHCI_TRNS_AUTO_CMD23 0x08
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_TRNS_READ 0x10
|
|
|
|
|
#define SDHCI_TRNS_MULTI 0x20
|
|
|
|
|
|
|
|
|
|
#define SDHCI_COMMAND 0x0E
|
|
|
|
|
#define SDHCI_CMD_RESP_MASK 0x03
|
|
|
|
|
#define SDHCI_CMD_CRC 0x08
|
|
|
|
|
#define SDHCI_CMD_INDEX 0x10
|
|
|
|
|
#define SDHCI_CMD_DATA 0x20
|
2011-03-21 05:22:14 +00:00
|
|
|
#define SDHCI_CMD_ABORTCMD 0xC0
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_CMD_RESP_NONE 0x00
|
|
|
|
|
#define SDHCI_CMD_RESP_LONG 0x01
|
|
|
|
|
#define SDHCI_CMD_RESP_SHORT 0x02
|
|
|
|
|
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
|
|
|
|
|
|
|
|
|
|
#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
|
2010-12-15 07:14:24 +00:00
|
|
|
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_RESPONSE 0x10
|
|
|
|
|
|
|
|
|
|
#define SDHCI_BUFFER 0x20
|
|
|
|
|
|
|
|
|
|
#define SDHCI_PRESENT_STATE 0x24
|
|
|
|
|
#define SDHCI_CMD_INHIBIT 0x00000001
|
|
|
|
|
#define SDHCI_DATA_INHIBIT 0x00000002
|
|
|
|
|
#define SDHCI_DOING_WRITE 0x00000100
|
|
|
|
|
#define SDHCI_DOING_READ 0x00000200
|
|
|
|
|
#define SDHCI_SPACE_AVAILABLE 0x00000400
|
|
|
|
|
#define SDHCI_DATA_AVAILABLE 0x00000800
|
|
|
|
|
#define SDHCI_CARD_PRESENT 0x00010000
|
|
|
|
|
#define SDHCI_WRITE_PROTECT 0x00080000
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_DATA_LVL_MASK 0x00F00000
|
|
|
|
|
#define SDHCI_DATA_LVL_SHIFT 20
|
2006-03-24 11:18:17 +00:00
|
|
|
|
2011-05-05 06:48:59 +00:00
|
|
|
#define SDHCI_HOST_CONTROL 0x28
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_CTRL_LED 0x01
|
|
|
|
|
#define SDHCI_CTRL_4BITBUS 0x02
|
2006-11-08 22:06:35 +00:00
|
|
|
#define SDHCI_CTRL_HISPD 0x04
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_CTRL_DMA_MASK 0x18
|
|
|
|
|
#define SDHCI_CTRL_SDMA 0x00
|
|
|
|
|
#define SDHCI_CTRL_ADMA1 0x08
|
|
|
|
|
#define SDHCI_CTRL_ADMA32 0x10
|
|
|
|
|
#define SDHCI_CTRL_ADMA64 0x18
|
2010-11-19 21:48:39 +00:00
|
|
|
#define SDHCI_CTRL_8BITBUS 0x20
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_POWER_CONTROL 0x29
|
2006-06-30 09:22:23 +00:00
|
|
|
#define SDHCI_POWER_ON 0x01
|
|
|
|
|
#define SDHCI_POWER_180 0x0A
|
|
|
|
|
#define SDHCI_POWER_300 0x0C
|
|
|
|
|
#define SDHCI_POWER_330 0x0E
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
|
|
|
|
|
|
2007-09-29 14:46:20 +00:00
|
|
|
#define SDHCI_WAKE_UP_CONTROL 0x2B
|
2010-11-04 22:20:39 +00:00
|
|
|
#define SDHCI_WAKE_ON_INT 0x01
|
|
|
|
|
#define SDHCI_WAKE_ON_INSERT 0x02
|
|
|
|
|
#define SDHCI_WAKE_ON_REMOVE 0x04
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_CLOCK_CONTROL 0x2C
|
|
|
|
|
#define SDHCI_DIVIDER_SHIFT 8
|
2010-08-05 23:10:01 +00:00
|
|
|
#define SDHCI_DIVIDER_HI_SHIFT 6
|
|
|
|
|
#define SDHCI_DIV_MASK 0xFF
|
|
|
|
|
#define SDHCI_DIV_MASK_LEN 8
|
|
|
|
|
#define SDHCI_DIV_HI_MASK 0x300
|
2011-05-05 06:49:06 +00:00
|
|
|
#define SDHCI_PROG_CLOCK_MODE 0x0020
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_CLOCK_CARD_EN 0x0004
|
|
|
|
|
#define SDHCI_CLOCK_INT_STABLE 0x0002
|
|
|
|
|
#define SDHCI_CLOCK_INT_EN 0x0001
|
|
|
|
|
|
|
|
|
|
#define SDHCI_TIMEOUT_CONTROL 0x2E
|
|
|
|
|
|
|
|
|
|
#define SDHCI_SOFTWARE_RESET 0x2F
|
|
|
|
|
#define SDHCI_RESET_ALL 0x01
|
|
|
|
|
#define SDHCI_RESET_CMD 0x02
|
|
|
|
|
#define SDHCI_RESET_DATA 0x04
|
|
|
|
|
|
|
|
|
|
#define SDHCI_INT_STATUS 0x30
|
|
|
|
|
#define SDHCI_INT_ENABLE 0x34
|
|
|
|
|
#define SDHCI_SIGNAL_ENABLE 0x38
|
|
|
|
|
#define SDHCI_INT_RESPONSE 0x00000001
|
|
|
|
|
#define SDHCI_INT_DATA_END 0x00000002
|
2012-12-04 02:41:28 +00:00
|
|
|
#define SDHCI_INT_BLK_GAP 0x00000004
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_INT_DMA_END 0x00000008
|
2006-07-02 15:50:59 +00:00
|
|
|
#define SDHCI_INT_SPACE_AVAIL 0x00000010
|
|
|
|
|
#define SDHCI_INT_DATA_AVAIL 0x00000020
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_INT_CARD_INSERT 0x00000040
|
|
|
|
|
#define SDHCI_INT_CARD_REMOVE 0x00000080
|
|
|
|
|
#define SDHCI_INT_CARD_INT 0x00000100
|
2007-07-20 16:20:36 +00:00
|
|
|
#define SDHCI_INT_ERROR 0x00008000
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_INT_TIMEOUT 0x00010000
|
|
|
|
|
#define SDHCI_INT_CRC 0x00020000
|
|
|
|
|
#define SDHCI_INT_END_BIT 0x00040000
|
|
|
|
|
#define SDHCI_INT_INDEX 0x00080000
|
|
|
|
|
#define SDHCI_INT_DATA_TIMEOUT 0x00100000
|
|
|
|
|
#define SDHCI_INT_DATA_CRC 0x00200000
|
|
|
|
|
#define SDHCI_INT_DATA_END_BIT 0x00400000
|
|
|
|
|
#define SDHCI_INT_BUS_POWER 0x00800000
|
|
|
|
|
#define SDHCI_INT_ACMD12ERR 0x01000000
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_INT_ADMA_ERROR 0x02000000
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
|
|
|
|
|
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
|
|
|
|
|
|
|
|
|
|
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
|
|
|
|
|
SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
|
|
|
|
|
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
|
2006-07-02 15:50:59 +00:00
|
|
|
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
|
2006-03-24 11:18:17 +00:00
|
|
|
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
|
2012-12-04 02:41:28 +00:00
|
|
|
SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
|
|
|
|
|
SDHCI_INT_BLK_GAP)
|
2009-03-16 21:13:48 +00:00
|
|
|
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_ACMD12_ERR 0x3C
|
|
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_HOST_CONTROL2 0x3E
|
2011-05-05 06:49:01 +00:00
|
|
|
#define SDHCI_CTRL_UHS_MASK 0x0007
|
|
|
|
|
#define SDHCI_CTRL_UHS_SDR12 0x0000
|
|
|
|
|
#define SDHCI_CTRL_UHS_SDR25 0x0001
|
|
|
|
|
#define SDHCI_CTRL_UHS_SDR50 0x0002
|
|
|
|
|
#define SDHCI_CTRL_UHS_SDR104 0x0003
|
|
|
|
|
#define SDHCI_CTRL_UHS_DDR50 0x0004
|
2012-01-06 04:26:39 +00:00
|
|
|
#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_CTRL_VDD_180 0x0008
|
2011-05-05 06:48:59 +00:00
|
|
|
#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
|
|
|
|
|
#define SDHCI_CTRL_DRV_TYPE_B 0x0000
|
|
|
|
|
#define SDHCI_CTRL_DRV_TYPE_A 0x0010
|
|
|
|
|
#define SDHCI_CTRL_DRV_TYPE_C 0x0020
|
|
|
|
|
#define SDHCI_CTRL_DRV_TYPE_D 0x0030
|
2011-05-05 06:49:04 +00:00
|
|
|
#define SDHCI_CTRL_EXEC_TUNING 0x0040
|
|
|
|
|
#define SDHCI_CTRL_TUNED_CLK 0x0080
|
2011-05-05 06:48:59 +00:00
|
|
|
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
#define SDHCI_CAPABILITIES 0x40
|
2006-06-30 09:22:25 +00:00
|
|
|
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
|
|
|
|
|
#define SDHCI_TIMEOUT_CLK_SHIFT 0
|
|
|
|
|
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
|
2010-08-20 18:02:36 +00:00
|
|
|
#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_CLOCK_BASE_SHIFT 8
|
2006-07-02 15:52:10 +00:00
|
|
|
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
|
|
|
|
#define SDHCI_MAX_BLOCK_SHIFT 16
|
2010-11-19 21:48:39 +00:00
|
|
|
#define SDHCI_CAN_DO_8BIT 0x00040000
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
|
|
|
|
#define SDHCI_CAN_DO_ADMA1 0x00100000
|
2006-11-08 22:06:35 +00:00
|
|
|
#define SDHCI_CAN_DO_HISPD 0x00200000
|
2009-09-22 23:45:30 +00:00
|
|
|
#define SDHCI_CAN_DO_SDMA 0x00400000
|
2006-06-30 09:22:23 +00:00
|
|
|
#define SDHCI_CAN_VDD_330 0x01000000
|
|
|
|
|
#define SDHCI_CAN_VDD_300 0x02000000
|
|
|
|
|
#define SDHCI_CAN_VDD_180 0x04000000
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_CAN_64BIT 0x10000000
|
2006-03-24 11:18:17 +00:00
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_SUPPORT_SDR50 0x00000001
|
|
|
|
|
#define SDHCI_SUPPORT_SDR104 0x00000002
|
|
|
|
|
#define SDHCI_SUPPORT_DDR50 0x00000004
|
2011-05-05 06:48:59 +00:00
|
|
|
#define SDHCI_DRIVER_TYPE_A 0x00000010
|
|
|
|
|
#define SDHCI_DRIVER_TYPE_C 0x00000020
|
|
|
|
|
#define SDHCI_DRIVER_TYPE_D 0x00000040
|
2011-05-05 06:49:07 +00:00
|
|
|
#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
|
|
|
|
|
#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
|
|
|
|
|
#define SDHCI_USE_SDR50_TUNING 0x00002000
|
|
|
|
|
#define SDHCI_RETUNING_MODE_MASK 0x0000C000
|
|
|
|
|
#define SDHCI_RETUNING_MODE_SHIFT 14
|
2011-05-05 06:49:06 +00:00
|
|
|
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
|
|
|
|
|
#define SDHCI_CLOCK_MUL_SHIFT 16
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
|
2010-11-30 05:55:23 +00:00
|
|
|
#define SDHCI_CAPABILITIES_1 0x44
|
2006-03-24 11:18:17 +00:00
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_MAX_CURRENT 0x48
|
2012-05-28 01:36:44 +00:00
|
|
|
#define SDHCI_MAX_CURRENT_LIMIT 0xFF
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 06:48:57 +00:00
|
|
|
#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
|
|
|
|
|
#define SDHCI_MAX_CURRENT_330_SHIFT 0
|
|
|
|
|
#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
|
|
|
|
|
#define SDHCI_MAX_CURRENT_300_SHIFT 8
|
|
|
|
|
#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
|
|
|
|
|
#define SDHCI_MAX_CURRENT_180_SHIFT 16
|
|
|
|
|
#define SDHCI_MAX_CURRENT_MULTIPLIER 4
|
2006-03-24 11:18:17 +00:00
|
|
|
|
|
|
|
|
/* 4C-4F reserved for more max current */
|
|
|
|
|
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_SET_ACMD12_ERROR 0x50
|
|
|
|
|
#define SDHCI_SET_INT_ERROR 0x52
|
|
|
|
|
|
|
|
|
|
#define SDHCI_ADMA_ERROR 0x54
|
|
|
|
|
|
|
|
|
|
/* 55-57 reserved */
|
|
|
|
|
|
|
|
|
|
#define SDHCI_ADMA_ADDRESS 0x58
|
|
|
|
|
|
|
|
|
|
/* 60-FB reserved */
|
2006-03-24 11:18:17 +00:00
|
|
|
|
2013-01-31 03:31:37 +00:00
|
|
|
#define SDHCI_PRESET_FOR_SDR12 0x66
|
|
|
|
|
#define SDHCI_PRESET_FOR_SDR25 0x68
|
|
|
|
|
#define SDHCI_PRESET_FOR_SDR50 0x6A
|
|
|
|
|
#define SDHCI_PRESET_FOR_SDR104 0x6C
|
|
|
|
|
#define SDHCI_PRESET_FOR_DDR50 0x6E
|
|
|
|
|
#define SDHCI_PRESET_DRV_MASK 0xC000
|
|
|
|
|
#define SDHCI_PRESET_DRV_SHIFT 14
|
|
|
|
|
#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
|
|
|
|
|
#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
|
|
|
|
|
#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
|
|
|
|
|
#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
|
|
|
|
|
|
2006-03-24 11:18:17 +00:00
|
|
|
#define SDHCI_SLOT_INT_STATUS 0xFC
|
|
|
|
|
|
|
|
|
|
#define SDHCI_HOST_VERSION 0xFE
|
2006-06-30 09:22:29 +00:00
|
|
|
#define SDHCI_VENDOR_VER_MASK 0xFF00
|
|
|
|
|
#define SDHCI_VENDOR_VER_SHIFT 8
|
|
|
|
|
#define SDHCI_SPEC_VER_MASK 0x00FF
|
|
|
|
|
#define SDHCI_SPEC_VER_SHIFT 0
|
2008-06-28 16:28:51 +00:00
|
|
|
#define SDHCI_SPEC_100 0
|
|
|
|
|
#define SDHCI_SPEC_200 1
|
2010-08-05 23:10:01 +00:00
|
|
|
#define SDHCI_SPEC_300 2
|
2006-03-24 11:18:17 +00:00
|
|
|
|
2010-09-20 19:15:18 +00:00
|
|
|
/*
|
|
|
|
|
* End of controller registers.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define SDHCI_MAX_DIV_SPEC_200 256
|
|
|
|
|
#define SDHCI_MAX_DIV_SPEC_300 2046
|
|
|
|
|
|
2011-04-12 13:36:18 +00:00
|
|
|
/*
|
|
|
|
|
* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
|
|
|
|
|
*/
|
|
|
|
|
#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
|
|
|
|
|
#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
|
|
|
|
|
|
2008-03-18 16:35:49 +00:00
|
|
|
struct sdhci_ops {
|
2009-03-16 21:13:46 +00:00
|
|
|
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
u32 (*read_l)(struct sdhci_host *host, int reg);
|
|
|
|
|
u16 (*read_w)(struct sdhci_host *host, int reg);
|
|
|
|
|
u8 (*read_b)(struct sdhci_host *host, int reg);
|
|
|
|
|
void (*write_l)(struct sdhci_host *host, u32 val, int reg);
|
|
|
|
|
void (*write_w)(struct sdhci_host *host, u16 val, int reg);
|
|
|
|
|
void (*write_b)(struct sdhci_host *host, u8 val, int reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
#endif
|
|
|
|
|
|
2009-03-16 21:13:59 +00:00
|
|
|
void (*set_clock)(struct sdhci_host *host, unsigned int clock);
|
|
|
|
|
|
2008-03-18 16:35:49 +00:00
|
|
|
int (*enable_dma)(struct sdhci_host *host);
|
2009-03-16 21:13:57 +00:00
|
|
|
unsigned int (*get_max_clock)(struct sdhci_host *host);
|
2009-07-29 22:04:16 +00:00
|
|
|
unsigned int (*get_min_clock)(struct sdhci_host *host);
|
2009-03-16 21:13:57 +00:00
|
|
|
unsigned int (*get_timeout_clock)(struct sdhci_host *host);
|
2013-01-21 11:02:27 +00:00
|
|
|
int (*platform_bus_width)(struct sdhci_host *host,
|
2010-11-19 21:48:39 +00:00
|
|
|
int width);
|
2010-09-23 15:24:32 +00:00
|
|
|
void (*platform_send_init_74_clocks)(struct sdhci_host *host,
|
|
|
|
|
u8 power_mode);
|
2010-10-15 10:21:01 +00:00
|
|
|
unsigned int (*get_ro)(struct sdhci_host *host);
|
2011-01-21 19:26:40 +00:00
|
|
|
void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
|
|
|
|
|
void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
|
2011-05-13 05:47:15 +00:00
|
|
|
int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
|
2011-08-29 13:42:12 +00:00
|
|
|
void (*hw_reset)(struct sdhci_host *host);
|
2012-02-06 05:43:59 +00:00
|
|
|
void (*platform_suspend)(struct sdhci_host *host);
|
|
|
|
|
void (*platform_resume)(struct sdhci_host *host);
|
2012-12-04 02:41:28 +00:00
|
|
|
void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
|
2012-10-25 05:47:19 +00:00
|
|
|
void (*platform_init)(struct sdhci_host *host);
|
2006-03-24 11:18:17 +00:00
|
|
|
};
|
2008-03-18 16:35:49 +00:00
|
|
|
|
2009-03-16 21:13:46 +00:00
|
|
|
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->write_l))
|
|
|
|
|
host->ops->write_l(host, val, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
writel(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->write_w))
|
|
|
|
|
host->ops->write_w(host, val, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
writew(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->write_b))
|
|
|
|
|
host->ops->write_b(host, val, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
writeb(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->read_l))
|
|
|
|
|
return host->ops->read_l(host, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
return readl(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->read_w))
|
|
|
|
|
return host->ops->read_w(host, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
return readw(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
sdhci: build fix: rename SDHCI I/O accessor functions
Unfortunately some architectures #define their read{b,w,l} and
write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of
the same names subject to preprocessing. This leads to the following
compiler error,
In file included from drivers/mmc/host/sdhci.c:26:
drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2
Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can
be enabled for architectures that implement their read{b,w,l} and
write{b,w,l} functions with macros.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Cc: Zhangfei Gao <zgao6@marvell.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-26 21:42:03 +00:00
|
|
|
if (unlikely(host->ops->read_b))
|
|
|
|
|
return host->ops->read_b(host, reg);
|
2009-03-16 21:13:46 +00:00
|
|
|
else
|
|
|
|
|
return readb(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
|
|
|
|
|
{
|
|
|
|
|
writel(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
|
|
|
|
|
{
|
|
|
|
|
writew(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
|
|
|
|
|
{
|
|
|
|
|
writeb(val, host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
|
|
|
|
return readl(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
|
|
|
|
return readw(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
|
|
|
|
|
{
|
|
|
|
|
return readb(host->ioaddr + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
|
2008-03-18 16:35:49 +00:00
|
|
|
|
|
|
|
|
extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
|
|
|
|
|
size_t priv_size);
|
|
|
|
|
extern void sdhci_free_host(struct sdhci_host *host);
|
|
|
|
|
|
|
|
|
|
static inline void *sdhci_priv(struct sdhci_host *host)
|
|
|
|
|
{
|
|
|
|
|
return (void *)host->private;
|
|
|
|
|
}
|
|
|
|
|
|
2010-08-11 01:01:58 +00:00
|
|
|
extern void sdhci_card_detect(struct sdhci_host *host);
|
2008-03-18 16:35:49 +00:00
|
|
|
extern int sdhci_add_host(struct sdhci_host *host);
|
2008-04-16 17:13:13 +00:00
|
|
|
extern void sdhci_remove_host(struct sdhci_host *host, int dead);
|
2008-03-18 16:35:49 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
2011-11-03 10:09:45 +00:00
|
|
|
extern int sdhci_suspend_host(struct sdhci_host *host);
|
2008-03-18 16:35:49 +00:00
|
|
|
extern int sdhci_resume_host(struct sdhci_host *host);
|
2010-11-04 22:20:39 +00:00
|
|
|
extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
|
2008-03-18 16:35:49 +00:00
|
|
|
#endif
|
2009-12-17 23:27:19 +00:00
|
|
|
|
2011-10-03 12:33:34 +00:00
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
|
|
|
extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
|
|
|
|
|
extern int sdhci_runtime_resume_host(struct sdhci_host *host);
|
|
|
|
|
#endif
|
|
|
|
|
|
mmc: sdhci: split up sdhci.h for sdhci-pltfm users
Some platforms based on sdhci-pltfm need to set their own quirks.
Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h.
This patch splits drivers/mmc/host/sdhci.h into two parts:
* drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors.
* include/linux/mmc/sdhci.h includes the sdhci structure and quirks.
Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should
now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h.
This patch avoids adding/changing the calls/flags in the
sdhci_pltfm_data structure. It has been tested on STM platforms
(e.g. STx7106, STx7108, STx5206) where the driver is configured
and used as shown in the example below:
[snip]
static int mmc_pad_resources(struct sdhci_host *sdhci)
{
if (!devm_stm_pad_claim(sdhci->mmc->parent,
&stx7108_mmc_pad_config,
dev_name(sdhci->mmc->parent)))
return -ENODEV;
return 0;
}
static struct sdhci_pltfm_data stx7108_mmc_platform_data = {
.init = mmc_pad_resources,
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
};
static struct platform_device stx7108_mmc_device = {
.name = "sdhci",
[snip]
Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h,
and no modifications should be needed on other sdhci-<XXX> drivers.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
2010-09-28 08:41:29 +00:00
|
|
|
#endif /* __SDHCI_HW_H */
|