2008-03-19 00:00:14 +00:00
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/*
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* Handle caching attributes in page tables (PAT)
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*
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* Authors: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* Suresh B Siddha <suresh.b.siddha@intel.com>
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*
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* Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen.
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*/
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/gfp.h>
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#include <linux/fs.h>
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#include <asm/msr.h>
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#include <asm/tlbflush.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/pat.h>
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#include <asm/e820.h>
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#include <asm/cacheflush.h>
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#include <asm/fcntl.h>
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#include <asm/mtrr.h>
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int pat_wc_enabled = 1;
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static u64 __read_mostly boot_pat_state;
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static int nopat(char *str)
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{
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pat_wc_enabled = 0;
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printk(KERN_INFO "x86: PAT support disabled.\n");
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return 0;
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}
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early_param("nopat", nopat);
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static int pat_known_cpu(void)
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{
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if (!pat_wc_enabled)
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return 0;
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2008-03-25 06:24:34 +00:00
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if (cpu_has_pat)
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return 1;
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2008-03-19 00:00:14 +00:00
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pat_wc_enabled = 0;
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printk(KERN_INFO "CPU and/or kernel does not support PAT.\n");
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return 0;
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}
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enum {
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PAT_UC = 0, /* uncached */
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PAT_WC = 1, /* Write combining */
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PAT_WT = 4, /* Write Through */
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PAT_WP = 5, /* Write Protected */
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PAT_WB = 6, /* Write Back (default) */
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PAT_UC_MINUS = 7, /* UC, but can be overriden by MTRR */
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};
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#define PAT(x,y) ((u64)PAT_ ## y << ((x)*8))
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void pat_init(void)
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{
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u64 pat;
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#ifndef CONFIG_X86_PAT
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nopat(NULL);
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#endif
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/* Boot CPU enables PAT based on CPU feature */
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if (!smp_processor_id() && !pat_known_cpu())
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return;
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/* APs enable PAT iff boot CPU has enabled it before */
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if (smp_processor_id() && !pat_wc_enabled)
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return;
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/* Set PWT to Write-Combining. All other bits stay the same */
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/*
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* PTE encoding used in Linux:
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* PAT
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* |PCD
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* ||PWT
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* |||
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* 000 WB _PAGE_CACHE_WB
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* 001 WC _PAGE_CACHE_WC
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* 010 UC- _PAGE_CACHE_UC_MINUS
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* 011 UC _PAGE_CACHE_UC
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* PAT bit unused
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*/
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pat = PAT(0,WB) | PAT(1,WC) | PAT(2,UC_MINUS) | PAT(3,UC) |
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PAT(4,WB) | PAT(5,WC) | PAT(6,UC_MINUS) | PAT(7,UC);
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/* Boot CPU check */
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if (!smp_processor_id()) {
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rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
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}
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wrmsrl(MSR_IA32_CR_PAT, pat);
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printk(KERN_INFO "x86 PAT enabled: cpu %d, old 0x%Lx, new 0x%Lx\n",
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smp_processor_id(), boot_pat_state, pat);
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}
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#undef PAT
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static char *cattr_name(unsigned long flags)
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{
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switch (flags & _PAGE_CACHE_MASK) {
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case _PAGE_CACHE_UC: return "uncached";
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case _PAGE_CACHE_UC_MINUS: return "uncached-minus";
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case _PAGE_CACHE_WB: return "write-back";
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case _PAGE_CACHE_WC: return "write-combining";
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default: return "broken";
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}
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}
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/*
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* The global memtype list keeps track of memory type for specific
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* physical memory areas. Conflicting memory types in different
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* mappings can cause CPU cache corruption. To avoid this we keep track.
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*
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* The list is sorted based on starting address and can contain multiple
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* entries for each address (this allows reference counting for overlapping
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* areas). All the aliases have the same cache attributes of course.
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* Zero attributes are represented as holes.
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*
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* Currently the data structure is a list because the number of mappings
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* are expected to be relatively small. If this should be a problem
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* it could be changed to a rbtree or similar.
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*
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* memtype_lock protects the whole list.
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*/
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struct memtype {
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u64 start;
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u64 end;
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unsigned long type;
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struct list_head nd;
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};
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static LIST_HEAD(memtype_list);
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static DEFINE_SPINLOCK(memtype_lock); /* protects memtype list */
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/*
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* Does intersection of PAT memory type and MTRR memory type and returns
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* the resulting memory type as PAT understands it.
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* (Type in pat and mtrr will not have same value)
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* The intersection is based on "Effective Memory Type" tables in IA-32
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* SDM vol 3a
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*/
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static int pat_x_mtrr_type(u64 start, u64 end, unsigned long prot,
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unsigned long *ret_prot)
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{
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unsigned long pat_type;
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u8 mtrr_type;
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mtrr_type = mtrr_type_lookup(start, end);
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if (mtrr_type == 0xFF) { /* MTRR not enabled */
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*ret_prot = prot;
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return 0;
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}
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if (mtrr_type == 0xFE) { /* MTRR match error */
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*ret_prot = _PAGE_CACHE_UC;
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return -1;
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}
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if (mtrr_type != MTRR_TYPE_UNCACHABLE &&
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mtrr_type != MTRR_TYPE_WRBACK &&
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mtrr_type != MTRR_TYPE_WRCOMB) { /* MTRR type unhandled */
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*ret_prot = _PAGE_CACHE_UC;
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return -1;
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}
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pat_type = prot & _PAGE_CACHE_MASK;
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prot &= (~_PAGE_CACHE_MASK);
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/* Currently doing intersection by hand. Optimize it later. */
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if (pat_type == _PAGE_CACHE_WC) {
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*ret_prot = prot | _PAGE_CACHE_WC;
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} else if (pat_type == _PAGE_CACHE_UC_MINUS) {
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*ret_prot = prot | _PAGE_CACHE_UC_MINUS;
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} else if (pat_type == _PAGE_CACHE_UC ||
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mtrr_type == MTRR_TYPE_UNCACHABLE) {
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*ret_prot = prot | _PAGE_CACHE_UC;
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} else if (mtrr_type == MTRR_TYPE_WRCOMB) {
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*ret_prot = prot | _PAGE_CACHE_WC;
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} else {
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*ret_prot = prot | _PAGE_CACHE_WB;
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}
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return 0;
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}
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int reserve_memtype(u64 start, u64 end, unsigned long req_type,
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unsigned long *ret_type)
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{
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struct memtype *new_entry = NULL;
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struct memtype *parse;
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unsigned long actual_type;
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int err = 0;
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/* Only track when pat_wc_enabled */
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if (!pat_wc_enabled) {
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if (ret_type)
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*ret_type = req_type;
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return 0;
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}
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/* Low ISA region is always mapped WB in page table. No need to track */
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if (start >= ISA_START_ADDRESS && (end - 1) <= ISA_END_ADDRESS) {
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if (ret_type)
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*ret_type = _PAGE_CACHE_WB;
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return 0;
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}
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req_type &= _PAGE_CACHE_MASK;
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err = pat_x_mtrr_type(start, end, req_type, &actual_type);
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if (err) {
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if (ret_type)
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*ret_type = actual_type;
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return -EINVAL;
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}
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new_entry = kmalloc(sizeof(struct memtype), GFP_KERNEL);
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if (!new_entry)
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return -ENOMEM;
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new_entry->start = start;
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new_entry->end = end;
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new_entry->type = actual_type;
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if (ret_type)
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*ret_type = actual_type;
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spin_lock(&memtype_lock);
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/* Search for existing mapping that overlaps the current range */
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list_for_each_entry(parse, &memtype_list, nd) {
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struct memtype *saved_ptr;
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if (parse->start >= end) {
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2008-03-19 00:00:25 +00:00
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printk("New Entry\n");
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2008-03-19 00:00:14 +00:00
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list_add(&new_entry->nd, parse->nd.prev);
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new_entry = NULL;
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break;
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}
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if (start <= parse->start && end >= parse->start) {
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if (actual_type != parse->type && ret_type) {
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actual_type = parse->type;
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*ret_type = actual_type;
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new_entry->type = actual_type;
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}
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if (actual_type != parse->type) {
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printk(
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KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
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current->comm, current->pid,
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start, end,
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cattr_name(actual_type),
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cattr_name(parse->type));
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err = -EBUSY;
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break;
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}
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saved_ptr = parse;
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/*
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* Check to see whether the request overlaps more
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* than one entry in the list
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*/
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list_for_each_entry_continue(parse, &memtype_list, nd) {
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if (end <= parse->start) {
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break;
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}
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if (actual_type != parse->type) {
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printk(
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KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
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current->comm, current->pid,
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start, end,
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cattr_name(actual_type),
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cattr_name(parse->type));
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err = -EBUSY;
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break;
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}
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}
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if (err) {
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break;
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}
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2008-03-19 00:00:25 +00:00
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printk("Overlap at 0x%Lx-0x%Lx\n",
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saved_ptr->start, saved_ptr->end);
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2008-03-19 00:00:14 +00:00
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/* No conflict. Go ahead and add this new entry */
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list_add(&new_entry->nd, saved_ptr->nd.prev);
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new_entry = NULL;
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break;
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}
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if (start < parse->end) {
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if (actual_type != parse->type && ret_type) {
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actual_type = parse->type;
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*ret_type = actual_type;
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new_entry->type = actual_type;
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}
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if (actual_type != parse->type) {
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printk(
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KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
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current->comm, current->pid,
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start, end,
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cattr_name(actual_type),
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cattr_name(parse->type));
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err = -EBUSY;
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break;
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}
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saved_ptr = parse;
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/*
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* Check to see whether the request overlaps more
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* than one entry in the list
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*/
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list_for_each_entry_continue(parse, &memtype_list, nd) {
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if (end <= parse->start) {
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break;
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}
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if (actual_type != parse->type) {
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printk(
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KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
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current->comm, current->pid,
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start, end,
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cattr_name(actual_type),
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cattr_name(parse->type));
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err = -EBUSY;
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break;
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}
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}
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if (err) {
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break;
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}
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2008-03-19 00:00:25 +00:00
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printk("Overlap at 0x%Lx-0x%Lx\n",
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saved_ptr->start, saved_ptr->end);
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2008-03-19 00:00:14 +00:00
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/* No conflict. Go ahead and add this new entry */
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list_add(&new_entry->nd, &saved_ptr->nd);
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new_entry = NULL;
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break;
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}
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}
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if (err) {
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2008-03-19 00:00:25 +00:00
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printk(
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"reserve_memtype failed 0x%Lx-0x%Lx, track %s, req %s\n",
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start, end, cattr_name(new_entry->type),
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cattr_name(req_type));
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2008-03-19 00:00:14 +00:00
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kfree(new_entry);
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spin_unlock(&memtype_lock);
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return err;
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}
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if (new_entry) {
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/* No conflict. Not yet added to the list. Add to the tail */
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list_add_tail(&new_entry->nd, &memtype_list);
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2008-03-19 00:00:25 +00:00
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printk("New Entry\n");
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}
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if (ret_type) {
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printk(
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"reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n",
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start, end, cattr_name(actual_type),
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cattr_name(req_type), cattr_name(*ret_type));
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} else {
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printk(
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|
|
|
"reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s\n",
|
|
|
|
start, end, cattr_name(actual_type),
|
|
|
|
cattr_name(req_type));
|
2008-03-19 00:00:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock(&memtype_lock);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
int free_memtype(u64 start, u64 end)
|
|
|
|
{
|
|
|
|
struct memtype *ml;
|
|
|
|
int err = -EINVAL;
|
|
|
|
|
|
|
|
/* Only track when pat_wc_enabled */
|
|
|
|
if (!pat_wc_enabled) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Low ISA region is always mapped WB. No need to track */
|
|
|
|
if (start >= ISA_START_ADDRESS && end <= ISA_END_ADDRESS) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock(&memtype_lock);
|
|
|
|
list_for_each_entry(ml, &memtype_list, nd) {
|
|
|
|
if (ml->start == start && ml->end == end) {
|
|
|
|
list_del(&ml->nd);
|
|
|
|
kfree(ml);
|
|
|
|
err = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock(&memtype_lock);
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
printk(KERN_DEBUG "%s:%d freeing invalid memtype %Lx-%Lx\n",
|
|
|
|
current->comm, current->pid, start, end);
|
|
|
|
}
|
2008-03-19 00:00:25 +00:00
|
|
|
|
|
|
|
printk( "free_memtype request 0x%Lx-0x%Lx\n", start, end);
|
2008-03-19 00:00:14 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2008-03-19 00:00:20 +00:00
|
|
|
|
|
|
|
/* /dev/mem interface. Use the previous mapping */
|
|
|
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|
|
|
unsigned long size, pgprot_t vma_prot)
|
|
|
|
{
|
|
|
|
return vma_prot;
|
|
|
|
}
|
|
|
|
|
|
|
|
int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
|
|
|
|
unsigned long size, pgprot_t *vma_prot)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (file->f_flags & O_SYNC) {
|
|
|
|
*vma_prot = pgprot_noncached(*vma_prot);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86_32
|
|
|
|
/*
|
|
|
|
* On the PPro and successors, the MTRRs are used to set
|
|
|
|
* memory types for physical addresses outside main memory,
|
|
|
|
* so blindly setting UC or PWT on those pages is wrong.
|
|
|
|
* For Pentiums and earlier, the surround logic should disable
|
|
|
|
* caching for the high addresses through the KEN pin, but
|
|
|
|
* we maintain the tradition of paranoia in this code.
|
|
|
|
*/
|
|
|
|
if (!pat_wc_enabled &&
|
|
|
|
! ( test_bit(X86_FEATURE_MTRR, boot_cpu_data.x86_capability) ||
|
|
|
|
test_bit(X86_FEATURE_K6_MTRR, boot_cpu_data.x86_capability) ||
|
|
|
|
test_bit(X86_FEATURE_CYRIX_ARR, boot_cpu_data.x86_capability) ||
|
|
|
|
test_bit(X86_FEATURE_CENTAUR_MCR, boot_cpu_data.x86_capability)) &&
|
|
|
|
(pfn << PAGE_SHIFT) >= __pa(high_memory)) {
|
|
|
|
*vma_prot = pgprot_noncached(*vma_prot);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|