34 lines
1.4 KiB
Text
34 lines
1.4 KiB
Text
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Notes on register bank usage in the kernel
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==========================================
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Introduction
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------------
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The SH-3 and SH-4 CPU families traditionally include a single partial register
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bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
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may have more full-featured banking or simply no such capabilities at all.
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SR.RB banking
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-------------
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In the case of this type of banking, banked registers are mapped directly to
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r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
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can still be used to reference the banked registers (as r0_bank ... r7_bank)
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when in the context of another bank. The developer must keep the SR.RB value
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in mind when writing code that utilizes these banked registers, for obvious
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reasons. Userspace is also not able to poke at the bank1 values, so these can
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be used rather effectively as scratch registers by the kernel.
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Presently the kernel uses several of these registers.
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- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
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registers when doing exception handling).
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- r2_bank (used to track the EXPEVT/INTEVT code)
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- Used by do_IRQ() and friends for doing irq mapping based off
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of the interrupt exception vector jump table offset
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- r6_bank (global interrupt mask)
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- The SR.IMASK interrupt handler makes use of this to set the
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interrupt priority level (used by local_irq_enable())
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- r7_bank (current)
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