2008-02-06 21:36:21 +00:00
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/* Freescale Enhanced Local Bus Controller NAND driver
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*
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2010-10-18 07:22:31 +00:00
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* Copyright © 2006-2007, 2010 Freescale Semiconductor
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2008-02-06 21:36:21 +00:00
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*
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* Authors: Nick Spence <nick.spence@freescale.com>,
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* Scott Wood <scottwood@freescale.com>
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2010-10-18 07:22:31 +00:00
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* Jack Lan <jack.lan@freescale.com>
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* Roy Zang <tie-fei.zang@freescale.com>
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2008-02-06 21:36:21 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/of_platform.h>
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2010-10-18 07:22:31 +00:00
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#include <linux/platform_device.h>
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2008-02-06 21:36:21 +00:00
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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2008-03-11 17:23:28 +00:00
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#include <asm/fsl_lbc.h>
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2008-02-06 21:36:21 +00:00
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#define MAX_BANKS 8
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#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
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#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
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/* mtd information per set */
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struct fsl_elbc_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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2010-10-18 07:22:31 +00:00
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struct fsl_lbc_ctrl *ctrl;
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2008-02-06 21:36:21 +00:00
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struct device *dev;
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int bank; /* Chip select bank number */
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u8 __iomem *vbase; /* Chip select base virtual address */
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int page_size; /* NAND page size (0=512, 1=2048) */
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unsigned int fmr; /* FCM Flash Mode Register value */
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};
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2011-03-31 01:57:33 +00:00
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/* Freescale eLBC FCM controller information */
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2008-02-06 21:36:21 +00:00
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2010-10-18 07:22:31 +00:00
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struct fsl_elbc_fcm_ctrl {
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2008-02-06 21:36:21 +00:00
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struct nand_hw_control controller;
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struct fsl_elbc_mtd *chips[MAX_BANKS];
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u8 __iomem *addr; /* Address of assigned FCM buffer */
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unsigned int page; /* Last page written to / read from */
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unsigned int read_bytes; /* Number of bytes read during command */
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unsigned int column; /* Saved column from SEQIN */
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unsigned int index; /* Pointer to next byte to 'read' */
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unsigned int status; /* status read from LTESR after last op */
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unsigned int mdr; /* UPM/FCM Data Register value */
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unsigned int use_mdr; /* Non zero if the MDR is to be set */
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unsigned int oob; /* Non zero if operating on OOB data */
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2010-10-18 07:22:31 +00:00
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unsigned int counter; /* counter for the initializations */
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2012-04-25 19:06:09 +00:00
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unsigned int max_bitflips; /* Saved during READ0 cmd */
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2008-02-06 21:36:21 +00:00
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};
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/* These map to the positions used by the FCM hardware ECC generator */
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/* Small Page FLASH with FMR[ECCM] = 0 */
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static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
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.eccbytes = 3,
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.eccpos = {6, 7, 8},
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.oobfree = { {0, 5}, {9, 7} },
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};
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/* Small Page FLASH with FMR[ECCM] = 1 */
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static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
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.eccbytes = 3,
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.eccpos = {8, 9, 10},
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.oobfree = { {0, 5}, {6, 2}, {11, 5} },
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};
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/* Large Page FLASH with FMR[ECCM] = 0 */
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static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
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.eccbytes = 12,
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.eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
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.oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
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};
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/* Large Page FLASH with FMR[ECCM] = 1 */
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static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
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.eccbytes = 12,
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.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
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.oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
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};
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[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
For large page chips, nand_bbt is looking into OOB area, and checking
for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
reserved for bbt means.
But ELBC driver is specifying ecclayout so that oobfree area starts at
offset 1, so only one byte left for the bbt purposes.
This causes problems with any OOB users, namely JFFS2: after first mount
JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
And on the next boot, NAND core will rescan for bad blocks, then will
see "0xff 0x19" pattern, and will mark all blocks as bad ones.
To fix the issue we should implement our own bad block pattern: just one
byte at OOB start. Though, this will work only for x8 chips. For x16
chips two bytes must be checked. Since ELBC driver does not support x16
NANDs (yet), we're safe for now.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2008-06-27 19:04:04 +00:00
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/*
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* fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
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* 1, so we have to adjust bad block pattern. This pattern should be used for
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* x8 chips only. So far hardware does not support x16 chips anyway.
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*/
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static u8 scan_ff_pattern[] = { 0xff, };
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static struct nand_bbt_descr largepage_memorybased = {
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.options = 0,
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.offs = 0,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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2008-06-27 19:04:13 +00:00
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/*
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* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
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* interfere with ECC positions, that's why we implement our own descriptors.
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* OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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2008-02-06 21:36:21 +00:00
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/*=================================*/
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/*
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* Set up the FCM hardware block and page address fields, and the fcm
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* structure addr field to point to the correct FCM buffer in memory
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*/
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static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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2010-10-18 07:22:31 +00:00
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struct fsl_lbc_ctrl *ctrl = priv->ctrl;
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2008-03-11 17:23:28 +00:00
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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2010-10-18 07:22:31 +00:00
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
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2008-02-06 21:36:21 +00:00
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int buf_num;
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->page = page_addr;
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2008-02-06 21:36:21 +00:00
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if (priv->page_size) {
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2011-12-09 09:42:54 +00:00
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/*
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* large page size chip : FPAR[PI] save the lowest 6 bits,
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* FBAR[BLK] save the other bits.
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*/
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out_be32(&lbc->fbar, page_addr >> 6);
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2008-02-06 21:36:21 +00:00
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out_be32(&lbc->fpar,
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((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
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(oob ? FPAR_LP_MS : 0) | column);
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buf_num = (page_addr & 1) << 2;
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} else {
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2011-12-09 09:42:54 +00:00
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/*
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* small page size chip : FPAR[PI] save the lowest 5 bits,
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* FBAR[BLK] save the other bits.
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*/
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out_be32(&lbc->fbar, page_addr >> 5);
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2008-02-06 21:36:21 +00:00
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out_be32(&lbc->fpar,
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((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
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(oob ? FPAR_SP_MS : 0) | column);
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buf_num = page_addr & 7;
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}
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
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elbc_fcm_ctrl->index = column;
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2008-02-06 21:36:21 +00:00
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/* for OOB data point to the second half of the buffer */
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if (oob)
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
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2008-02-06 21:36:21 +00:00
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2010-10-18 07:22:31 +00:00
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dev_vdbg(priv->dev, "set_addr: bank=%d, "
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"elbc_fcm_ctrl->addr=0x%p (0x%p), "
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2008-02-06 21:36:21 +00:00
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"index %x, pes %d ps %d\n",
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2010-10-18 07:22:31 +00:00
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buf_num, elbc_fcm_ctrl->addr, priv->vbase,
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elbc_fcm_ctrl->index,
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2008-02-06 21:36:21 +00:00
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chip->phys_erase_shift, chip->page_shift);
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}
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/*
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* execute FCM command and wait for it to complete
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*/
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static int fsl_elbc_run_command(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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2010-10-18 07:22:31 +00:00
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struct fsl_lbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
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2008-03-11 17:23:28 +00:00
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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2008-02-06 21:36:21 +00:00
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/* Setup the FMR[OP] to execute without write protection */
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out_be32(&lbc->fmr, priv->fmr | 3);
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2010-10-18 07:22:31 +00:00
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if (elbc_fcm_ctrl->use_mdr)
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out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
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2008-02-06 21:36:21 +00:00
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2010-10-18 07:22:31 +00:00
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dev_vdbg(priv->dev,
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2008-02-06 21:36:21 +00:00
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"fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
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in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
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2010-10-18 07:22:31 +00:00
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dev_vdbg(priv->dev,
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2008-02-06 21:36:21 +00:00
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"fsl_elbc_run_command: fbar=%08x fpar=%08x "
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"fbcr=%08x bank=%d\n",
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in_be32(&lbc->fbar), in_be32(&lbc->fpar),
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in_be32(&lbc->fbcr), priv->bank);
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2008-03-19 17:40:15 +00:00
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ctrl->irq_status = 0;
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2008-02-06 21:36:21 +00:00
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/* execute special operation */
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out_be32(&lbc->lsor, priv->bank);
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/* wait for FCM complete flag or timeout */
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wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
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FCM_TIMEOUT_MSECS * HZ/1000);
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->status = ctrl->irq_status;
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2008-02-06 21:36:21 +00:00
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/* store mdr value in case it was needed */
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2010-10-18 07:22:31 +00:00
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if (elbc_fcm_ctrl->use_mdr)
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elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
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2008-02-06 21:36:21 +00:00
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->use_mdr = 0;
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2008-02-06 21:36:21 +00:00
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2010-10-18 07:22:31 +00:00
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if (elbc_fcm_ctrl->status != LTESR_CC) {
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dev_info(priv->dev,
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2009-11-13 20:14:15 +00:00
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"command failed: fir %x fcr %x status %x mdr %x\n",
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in_be32(&lbc->fir), in_be32(&lbc->fcr),
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2010-10-18 07:22:31 +00:00
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elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
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2009-11-13 20:14:15 +00:00
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return -EIO;
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}
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2008-02-06 21:36:21 +00:00
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2011-07-26 20:07:42 +00:00
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if (chip->ecc.mode != NAND_ECC_HW)
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return 0;
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2012-04-25 19:06:09 +00:00
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elbc_fcm_ctrl->max_bitflips = 0;
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2011-07-26 20:07:42 +00:00
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if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
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uint32_t lteccr = in_be32(&lbc->lteccr);
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/*
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* if command was a full page read and the ELBC
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* has the LTECCR register, then bits 12-15 (ppc order) of
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* LTECCR indicates which 512 byte sub-pages had fixed errors.
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* bits 28-31 are uncorrectable errors, marked elsewhere.
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* for small page nand only 1 bit is used.
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* if the ELBC doesn't have the lteccr register it reads 0
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2012-04-25 19:06:09 +00:00
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* FIXME: 4 bits can be corrected on NANDs with 2k pages, so
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* count the number of sub-pages with bitflips and update
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* ecc_stats.corrected accordingly.
|
2011-07-26 20:07:42 +00:00
|
|
|
*/
|
|
|
|
if (lteccr & 0x000F000F)
|
|
|
|
out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
|
2012-04-25 19:06:09 +00:00
|
|
|
if (lteccr & 0x000F0000) {
|
2011-07-26 20:07:42 +00:00
|
|
|
mtd->ecc_stats.corrected++;
|
2012-04-25 19:06:09 +00:00
|
|
|
elbc_fcm_ctrl->max_bitflips = 1;
|
|
|
|
}
|
2011-07-26 20:07:42 +00:00
|
|
|
}
|
|
|
|
|
2009-11-13 20:14:15 +00:00
|
|
|
return 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
|
|
|
|
{
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl;
|
2008-03-11 17:23:28 +00:00
|
|
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
if (priv->page_size) {
|
|
|
|
out_be32(&lbc->fir,
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_CA << FIR_OP1_SHIFT) |
|
|
|
|
(FIR_OP_PA << FIR_OP2_SHIFT) |
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM1 << FIR_OP3_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_RBW << FIR_OP4_SHIFT));
|
|
|
|
|
|
|
|
out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
|
|
|
|
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
|
|
|
|
} else {
|
|
|
|
out_be32(&lbc->fir,
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_CA << FIR_OP1_SHIFT) |
|
|
|
|
(FIR_OP_PA << FIR_OP2_SHIFT) |
|
|
|
|
(FIR_OP_RBW << FIR_OP3_SHIFT));
|
|
|
|
|
|
|
|
if (oob)
|
|
|
|
out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
|
|
|
|
else
|
|
|
|
out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* cmdfunc send commands to the FCM */
|
|
|
|
static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
|
|
|
int column, int page_addr)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl;
|
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
|
2008-03-11 17:23:28 +00:00
|
|
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->use_mdr = 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
/* clear the read buffer */
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->read_bytes = 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
if (command != NAND_CMD_PAGEPROG)
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->index = 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
switch (command) {
|
|
|
|
/* READ0 and READ1 read the entire buffer to use hardware ECC. */
|
|
|
|
case NAND_CMD_READ1:
|
|
|
|
column += 256;
|
|
|
|
|
|
|
|
/* fall-through */
|
|
|
|
case NAND_CMD_READ0:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
|
|
|
|
" 0x%x, column: 0x%x.\n", page_addr, column);
|
|
|
|
|
|
|
|
|
|
|
|
out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
|
|
|
|
set_addr(mtd, 0, page_addr, 0);
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
|
|
|
|
elbc_fcm_ctrl->index += column;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
fsl_elbc_do_read(chip, 0);
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* READOOB reads only the OOB because no ECC is performed. */
|
|
|
|
case NAND_CMD_READOOB:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_vdbg(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
|
|
|
|
" 0x%x, column: 0x%x.\n", page_addr, column);
|
|
|
|
|
|
|
|
out_be32(&lbc->fbcr, mtd->oobsize - column);
|
|
|
|
set_addr(mtd, column, page_addr, 1);
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
fsl_elbc_do_read(chip, 1);
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NAND_CMD_READID:
|
2011-12-12 09:40:53 +00:00
|
|
|
case NAND_CMD_PARAM:
|
|
|
|
dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2009-11-13 20:13:01 +00:00
|
|
|
out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_UA << FIR_OP1_SHIFT) |
|
|
|
|
(FIR_OP_RBW << FIR_OP2_SHIFT));
|
2011-12-12 09:40:53 +00:00
|
|
|
out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
|
|
|
|
/*
|
|
|
|
* although currently it's 8 bytes for READID, we always read
|
|
|
|
* the maximum 256 bytes(for PARAM)
|
|
|
|
*/
|
|
|
|
out_be32(&lbc->fbcr, 256);
|
|
|
|
elbc_fcm_ctrl->read_bytes = 256;
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->use_mdr = 1;
|
2011-12-12 09:40:53 +00:00
|
|
|
elbc_fcm_ctrl->mdr = column;
|
2008-02-06 21:36:21 +00:00
|
|
|
set_addr(mtd, 0, 0, 0);
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* ERASE1 stores the block and page address */
|
|
|
|
case NAND_CMD_ERASE1:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_vdbg(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
|
|
|
|
"page_addr: 0x%x.\n", page_addr);
|
|
|
|
set_addr(mtd, 0, page_addr, 0);
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* ERASE2 uses the block and page address from ERASE1 */
|
|
|
|
case NAND_CMD_ERASE2:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
out_be32(&lbc->fir,
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_PA << FIR_OP1_SHIFT) |
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM2 << FIR_OP2_SHIFT) |
|
|
|
|
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
|
|
|
|
(FIR_OP_RS << FIR_OP4_SHIFT));
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
out_be32(&lbc->fcr,
|
|
|
|
(NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
|
2009-11-13 20:13:01 +00:00
|
|
|
(NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
|
|
|
|
(NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
out_be32(&lbc->fbcr, 0);
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->read_bytes = 0;
|
|
|
|
elbc_fcm_ctrl->use_mdr = 1;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* SEQIN sets up the addr buffer and all registers except the length */
|
|
|
|
case NAND_CMD_SEQIN: {
|
|
|
|
__be32 fcr;
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_vdbg(priv->dev,
|
|
|
|
"fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
|
2008-02-06 21:36:21 +00:00
|
|
|
"page_addr: 0x%x, column: 0x%x.\n",
|
|
|
|
page_addr, column);
|
|
|
|
|
2010-11-23 17:38:36 +00:00
|
|
|
elbc_fcm_ctrl->column = column;
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->use_mdr = 1;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2011-12-04 04:31:36 +00:00
|
|
|
if (column >= mtd->writesize) {
|
|
|
|
/* OOB area */
|
|
|
|
column -= mtd->writesize;
|
|
|
|
elbc_fcm_ctrl->oob = 1;
|
|
|
|
} else {
|
|
|
|
WARN_ON(column != 0);
|
|
|
|
elbc_fcm_ctrl->oob = 0;
|
|
|
|
}
|
|
|
|
|
2009-11-13 20:13:01 +00:00
|
|
|
fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
|
|
|
|
(NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
|
|
|
|
(NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
|
2008-04-04 22:06:05 +00:00
|
|
|
|
2009-11-13 20:13:01 +00:00
|
|
|
if (priv->page_size) {
|
2008-02-06 21:36:21 +00:00
|
|
|
out_be32(&lbc->fir,
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM2 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_CA << FIR_OP1_SHIFT) |
|
|
|
|
(FIR_OP_PA << FIR_OP2_SHIFT) |
|
|
|
|
(FIR_OP_WB << FIR_OP3_SHIFT) |
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM3 << FIR_OP4_SHIFT) |
|
|
|
|
(FIR_OP_CW1 << FIR_OP5_SHIFT) |
|
|
|
|
(FIR_OP_RS << FIR_OP6_SHIFT));
|
2008-02-06 21:36:21 +00:00
|
|
|
} else {
|
|
|
|
out_be32(&lbc->fir,
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
2008-02-06 21:36:21 +00:00
|
|
|
(FIR_OP_CM2 << FIR_OP1_SHIFT) |
|
|
|
|
(FIR_OP_CA << FIR_OP2_SHIFT) |
|
|
|
|
(FIR_OP_PA << FIR_OP3_SHIFT) |
|
|
|
|
(FIR_OP_WB << FIR_OP4_SHIFT) |
|
2009-11-13 20:13:01 +00:00
|
|
|
(FIR_OP_CM3 << FIR_OP5_SHIFT) |
|
|
|
|
(FIR_OP_CW1 << FIR_OP6_SHIFT) |
|
|
|
|
(FIR_OP_RS << FIR_OP7_SHIFT));
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2011-12-04 04:31:36 +00:00
|
|
|
if (elbc_fcm_ctrl->oob)
|
2008-02-06 21:36:21 +00:00
|
|
|
/* OOB area --> READOOB */
|
|
|
|
fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
|
2011-12-04 04:31:36 +00:00
|
|
|
else
|
2008-02-06 21:36:21 +00:00
|
|
|
/* First 256 bytes --> READ0 */
|
|
|
|
fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
|
|
|
|
}
|
|
|
|
|
|
|
|
out_be32(&lbc->fcr, fcr);
|
2010-10-18 07:22:31 +00:00
|
|
|
set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
|
2008-02-06 21:36:21 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
|
|
|
|
case NAND_CMD_PAGEPROG: {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_vdbg(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
|
2010-10-18 07:22:31 +00:00
|
|
|
"writing %d bytes.\n", elbc_fcm_ctrl->index);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
/* if the write did not start at 0 or is not a full page
|
|
|
|
* then set the exact length, otherwise use a full page
|
|
|
|
* write so the HW generates the ECC.
|
|
|
|
*/
|
2010-10-18 07:22:31 +00:00
|
|
|
if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
|
2011-07-05 23:14:48 +00:00
|
|
|
elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
|
2011-12-04 04:31:37 +00:00
|
|
|
out_be32(&lbc->fbcr,
|
|
|
|
elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
|
2011-07-05 23:14:48 +00:00
|
|
|
else
|
2008-02-06 21:36:21 +00:00
|
|
|
out_be32(&lbc->fbcr, 0);
|
|
|
|
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* CMD_STATUS must read the status byte while CEB is active */
|
|
|
|
/* Note - it does not wait for the ready line */
|
|
|
|
case NAND_CMD_STATUS:
|
|
|
|
out_be32(&lbc->fir,
|
|
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
|
|
|
(FIR_OP_RBW << FIR_OP1_SHIFT));
|
|
|
|
out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
|
|
|
|
out_be32(&lbc->fbcr, 1);
|
|
|
|
set_addr(mtd, 0, 0, 0);
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->read_bytes = 1;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
|
|
|
|
/* The chip always seems to report that it is
|
|
|
|
* write-protected, even when it is not.
|
|
|
|
*/
|
2010-10-18 07:22:31 +00:00
|
|
|
setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
|
2008-02-06 21:36:21 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* RESET without waiting for the ready line */
|
|
|
|
case NAND_CMD_RESET:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
|
|
|
|
out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
|
|
|
|
|
|
default:
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
|
|
|
|
command);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
|
|
|
|
{
|
|
|
|
/* The hardware does not seem to support multiple
|
|
|
|
* chips per bank.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write buf to the FCM Controller Data Buffer
|
|
|
|
*/
|
|
|
|
static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
unsigned int bufsize = mtd->writesize + mtd->oobsize;
|
|
|
|
|
2008-03-28 19:10:54 +00:00
|
|
|
if (len <= 0) {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev, "write_buf of %d bytes", len);
|
|
|
|
elbc_fcm_ctrl->status = 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
|
|
|
|
dev_err(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"write_buf beyond end of buffer "
|
|
|
|
"(%d requested, %u available)\n",
|
2010-10-18 07:22:31 +00:00
|
|
|
len, bufsize - elbc_fcm_ctrl->index);
|
|
|
|
len = bufsize - elbc_fcm_ctrl->index;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
|
2008-03-28 19:10:54 +00:00
|
|
|
/*
|
|
|
|
* This is workaround for the weird elbc hangs during nand write,
|
|
|
|
* Scott Wood says: "...perhaps difference in how long it takes a
|
|
|
|
* write to make it through the localbus compared to a write to IMMR
|
|
|
|
* is causing problems, and sync isn't helping for some reason."
|
|
|
|
* Reading back the last byte helps though.
|
|
|
|
*/
|
2010-10-18 07:22:31 +00:00
|
|
|
in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
|
2008-03-28 19:10:54 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->index += len;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* read a byte from either the FCM hardware buffer if it has any data left
|
|
|
|
* otherwise issue a command to read a single byte.
|
|
|
|
*/
|
|
|
|
static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
/* If there are still bytes in the FCM, then use the next byte. */
|
2010-10-18 07:22:31 +00:00
|
|
|
if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
|
|
|
|
return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev, "read_byte beyond end of buffer\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
return ERR_BYTE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read from the FCM Controller Data Buffer
|
|
|
|
*/
|
|
|
|
static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
int avail;
|
|
|
|
|
|
|
|
if (len < 0)
|
|
|
|
return;
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
avail = min((unsigned int)len,
|
|
|
|
elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
|
|
|
|
memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
|
|
|
|
elbc_fcm_ctrl->index += avail;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
if (len > avail)
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"read_buf beyond end of buffer "
|
|
|
|
"(%d requested, %d available)\n",
|
|
|
|
len, avail);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Verify buffer against the FCM Controller Data Buffer
|
|
|
|
*/
|
|
|
|
static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (len < 0) {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev, "write_buf of %d bytes", len);
|
2008-02-06 21:36:21 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
if ((unsigned int)len >
|
|
|
|
elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
|
|
|
|
dev_err(priv->dev,
|
|
|
|
"verify_buf beyond end of buffer "
|
|
|
|
"(%d requested, %u available)\n",
|
|
|
|
len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
|
2008-02-06 21:36:21 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < len; i++)
|
2010-10-18 07:22:31 +00:00
|
|
|
if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
|
|
|
|
!= buf[i])
|
2008-02-06 21:36:21 +00:00
|
|
|
break;
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->index += len;
|
|
|
|
return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This function is called after Program and Erase Operations to
|
|
|
|
* check for success or failure.
|
|
|
|
*/
|
|
|
|
static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|
|
|
{
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
if (elbc_fcm_ctrl->status != LTESR_CC)
|
2008-02-06 21:36:21 +00:00
|
|
|
return NAND_STATUS_FAIL;
|
|
|
|
|
|
|
|
/* The chip always seems to report that it is
|
|
|
|
* write-protected, even when it is not.
|
|
|
|
*/
|
2010-10-18 07:22:31 +00:00
|
|
|
return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl;
|
2008-03-11 17:23:28 +00:00
|
|
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
|
2008-02-06 21:36:21 +00:00
|
|
|
unsigned int al;
|
|
|
|
|
|
|
|
/* calculate FMR Address Length field */
|
|
|
|
al = 0;
|
|
|
|
if (chip->pagemask & 0xffff0000)
|
|
|
|
al++;
|
|
|
|
if (chip->pagemask & 0xff000000)
|
|
|
|
al++;
|
|
|
|
|
2011-12-12 09:40:52 +00:00
|
|
|
priv->fmr |= al << FMR_AL_SHIFT;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->numchips);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->chipsize);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->pagemask);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->chip_delay);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->badblockpos);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->chip_shift);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->page_shift);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->phys_erase_shift);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecclayout);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecc.mode);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecc.steps);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecc.bytes);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecc.total);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->ecc.layout);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
|
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
|
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
mtd->erasesize);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
mtd->writesize);
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
|
2008-02-06 21:36:21 +00:00
|
|
|
mtd->oobsize);
|
|
|
|
|
|
|
|
/* adjust Option Register and ECC to match Flash page size */
|
|
|
|
if (mtd->writesize == 512) {
|
|
|
|
priv->page_size = 0;
|
2008-03-19 17:40:15 +00:00
|
|
|
clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
|
2008-02-06 21:36:21 +00:00
|
|
|
} else if (mtd->writesize == 2048) {
|
|
|
|
priv->page_size = 1;
|
|
|
|
setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
|
|
|
|
/* adjust ecc setup if needed */
|
|
|
|
if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
|
|
|
|
BR_DECC_CHK_GEN) {
|
|
|
|
chip->ecc.size = 512;
|
|
|
|
chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
|
|
|
|
&fsl_elbc_oob_lp_eccm1 :
|
|
|
|
&fsl_elbc_oob_lp_eccm0;
|
[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
For large page chips, nand_bbt is looking into OOB area, and checking
for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
reserved for bbt means.
But ELBC driver is specifying ecclayout so that oobfree area starts at
offset 1, so only one byte left for the bbt purposes.
This causes problems with any OOB users, namely JFFS2: after first mount
JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
And on the next boot, NAND core will rescan for bad blocks, then will
see "0xff 0x19" pattern, and will mark all blocks as bad ones.
To fix the issue we should implement our own bad block pattern: just one
byte at OOB start. Though, this will work only for x8 chips. For x16
chips two bytes must be checked. Since ELBC driver does not support x16
NANDs (yet), we're safe for now.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2008-06-27 19:04:04 +00:00
|
|
|
chip->badblock_pattern = &largepage_memorybased;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
} else {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(priv->dev,
|
2008-02-06 21:36:21 +00:00
|
|
|
"fsl_elbc_init: page size %d is not supported\n",
|
|
|
|
mtd->writesize);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-02 17:14:55 +00:00
|
|
|
static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
|
|
uint8_t *buf, int oob_required, int page)
|
2008-02-06 21:36:21 +00:00
|
|
|
{
|
2012-04-25 19:06:09 +00:00
|
|
|
struct fsl_elbc_mtd *priv = chip->priv;
|
|
|
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl;
|
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
|
|
|
|
|
2008-02-06 21:36:21 +00:00
|
|
|
fsl_elbc_read_buf(mtd, buf, mtd->writesize);
|
2012-05-02 17:15:00 +00:00
|
|
|
if (oob_required)
|
|
|
|
fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
|
|
|
|
mtd->ecc_stats.failed++;
|
|
|
|
|
2012-04-25 19:06:09 +00:00
|
|
|
return elbc_fcm_ctrl->max_bitflips;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* ECC will be calculated automatically, and errors will be detected in
|
|
|
|
* waitfunc.
|
|
|
|
*/
|
2012-06-25 10:07:45 +00:00
|
|
|
static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
2012-05-02 17:14:55 +00:00
|
|
|
const uint8_t *buf, int oob_required)
|
2008-02-06 21:36:21 +00:00
|
|
|
{
|
|
|
|
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
|
|
|
|
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
2012-06-25 10:07:45 +00:00
|
|
|
|
|
|
|
return 0;
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
|
|
|
|
{
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl;
|
2008-03-11 17:23:28 +00:00
|
|
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
struct nand_chip *chip = &priv->chip;
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
|
|
|
|
|
|
|
|
/* Fill in fsl_elbc_mtd structure */
|
|
|
|
priv->mtd.priv = chip;
|
|
|
|
priv->mtd.owner = THIS_MODULE;
|
2008-12-09 06:32:31 +00:00
|
|
|
|
2011-12-12 09:40:52 +00:00
|
|
|
/* set timeout to maximum */
|
|
|
|
priv->fmr = 15 << FMR_CWTO_SHIFT;
|
|
|
|
if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
|
|
|
|
priv->fmr |= FMR_ECCM;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
/* fill in nand_chip structure */
|
|
|
|
/* set up function call table */
|
|
|
|
chip->read_byte = fsl_elbc_read_byte;
|
|
|
|
chip->write_buf = fsl_elbc_write_buf;
|
|
|
|
chip->read_buf = fsl_elbc_read_buf;
|
|
|
|
chip->verify_buf = fsl_elbc_verify_buf;
|
|
|
|
chip->select_chip = fsl_elbc_select_chip;
|
|
|
|
chip->cmdfunc = fsl_elbc_cmdfunc;
|
|
|
|
chip->waitfunc = fsl_elbc_wait;
|
|
|
|
|
2008-06-27 19:04:13 +00:00
|
|
|
chip->bbt_td = &bbt_main_descr;
|
|
|
|
chip->bbt_md = &bbt_mirror_descr;
|
|
|
|
|
2008-02-06 21:36:21 +00:00
|
|
|
/* set up nand options */
|
2011-05-31 23:31:23 +00:00
|
|
|
chip->bbt_options = NAND_BBT_USE_FLASH;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
chip->controller = &elbc_fcm_ctrl->controller;
|
2008-02-06 21:36:21 +00:00
|
|
|
chip->priv = priv;
|
|
|
|
|
|
|
|
chip->ecc.read_page = fsl_elbc_read_page;
|
|
|
|
chip->ecc.write_page = fsl_elbc_write_page;
|
|
|
|
|
|
|
|
/* If CS Base Register selects full hardware ECC then use it */
|
|
|
|
if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
|
|
|
|
BR_DECC_CHK_GEN) {
|
|
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
|
|
/* put in small page settings and adjust later if needed */
|
|
|
|
chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
|
|
|
|
&fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
|
|
|
|
chip->ecc.size = 512;
|
|
|
|
chip->ecc.bytes = 3;
|
2012-03-11 21:21:11 +00:00
|
|
|
chip->ecc.strength = 1;
|
2008-02-06 21:36:21 +00:00
|
|
|
} else {
|
|
|
|
/* otherwise fall back to default software ECC */
|
|
|
|
chip->ecc.mode = NAND_ECC_SOFT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
|
|
|
|
{
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
|
2008-02-06 21:36:21 +00:00
|
|
|
nand_release(&priv->mtd);
|
|
|
|
|
[MTD] [NAND] fsl_elbc_nand: fix mtd name
Currently fsl_elbc_nand doesn't initialize mtd->name, and this causes
nand_get_flash_type() to assign name that is equal to chip type, like
this:
root@b1:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00800000 00010000 "fe000000.flash"
mtd1: 02000000 00004000 "NAND 32MiB 3,3V 8-bit"
mtd0 is physmap_of flash (normal name), and mtd1 is fsl_elbc_nand.
Despite inconsistency, with mtd name like this specifying paritions
from the kernel command line becomes a torture (though, I didn't tried
and not sure if mtdparts= can handle spaces at all). Plus, this causes
real bugs when multiple fsl_elbc_nand chips registered.
With this patch applied fsl_elbc_nand chip will have proper name:
root@b1:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00800000 00010000 "fe000000.flash"
mtd1: 02000000 00004000 "e0600000.flash"
p.s. We can't use priv->dev->bus_id as in physmap_of, because
fsl_elbc_nand pretends to be a localbus controller, so its bus_id is
"address.localbus", which is incorrect and thus will also not work
for multiple chips.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2008-03-18 16:34:03 +00:00
|
|
|
kfree(priv->mtd.name);
|
|
|
|
|
2008-02-06 21:36:21 +00:00
|
|
|
if (priv->vbase)
|
|
|
|
iounmap(priv->vbase);
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
elbc_fcm_ctrl->chips[priv->bank] = NULL;
|
2008-02-06 21:36:21 +00:00
|
|
|
kfree(priv);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
static DEFINE_MUTEX(fsl_elbc_nand_mutex);
|
|
|
|
|
|
|
|
static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
|
2008-02-06 21:36:21 +00:00
|
|
|
{
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_lbc_regs __iomem *lbc;
|
2008-02-06 21:36:21 +00:00
|
|
|
struct fsl_elbc_mtd *priv;
|
|
|
|
struct resource res;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
|
2008-02-06 21:36:21 +00:00
|
|
|
static const char *part_probe_types[]
|
2011-05-29 21:02:22 +00:00
|
|
|
= { "cmdlinepart", "RedBoot", "ofpart", NULL };
|
2008-02-06 21:36:21 +00:00
|
|
|
int ret;
|
|
|
|
int bank;
|
2010-10-18 07:22:31 +00:00
|
|
|
struct device *dev;
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
2011-05-29 21:02:22 +00:00
|
|
|
struct mtd_part_parser_data ppdata;
|
2010-10-18 07:22:31 +00:00
|
|
|
|
2011-05-29 21:02:22 +00:00
|
|
|
ppdata.of_node = pdev->dev.of_node;
|
2010-10-18 07:22:31 +00:00
|
|
|
if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
|
|
|
|
return -ENODEV;
|
|
|
|
lbc = fsl_lbc_ctrl_dev->regs;
|
|
|
|
dev = fsl_lbc_ctrl_dev->dev;
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
/* get, allocate and map the memory resource */
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
|
|
if (ret) {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(dev, "failed to get resource\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* find which chip select it is connected to */
|
|
|
|
for (bank = 0; bank < MAX_BANKS; bank++)
|
|
|
|
if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
|
|
|
|
(in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
|
|
|
|
(in_be32(&lbc->bank[bank].br) &
|
|
|
|
in_be32(&lbc->bank[bank].or) & BR_BA)
|
2010-10-18 07:22:32 +00:00
|
|
|
== fsl_lbc_addr(res.start))
|
2008-02-06 21:36:21 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (bank >= MAX_BANKS) {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(dev, "address did not match any chip selects\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
mutex_lock(&fsl_elbc_nand_mutex);
|
|
|
|
if (!fsl_lbc_ctrl_dev->nand) {
|
|
|
|
elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
|
|
|
|
if (!elbc_fcm_ctrl) {
|
|
|
|
dev_err(dev, "failed to allocate memory\n");
|
|
|
|
mutex_unlock(&fsl_elbc_nand_mutex);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
elbc_fcm_ctrl->counter++;
|
|
|
|
|
|
|
|
spin_lock_init(&elbc_fcm_ctrl->controller.lock);
|
|
|
|
init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
|
|
|
|
fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
|
|
|
|
} else {
|
|
|
|
elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
|
|
|
|
}
|
|
|
|
mutex_unlock(&fsl_elbc_nand_mutex);
|
|
|
|
|
|
|
|
elbc_fcm_ctrl->chips[bank] = priv;
|
2008-02-06 21:36:21 +00:00
|
|
|
priv->bank = bank;
|
2010-10-18 07:22:31 +00:00
|
|
|
priv->ctrl = fsl_lbc_ctrl_dev;
|
2012-06-06 23:36:39 +00:00
|
|
|
priv->dev = &pdev->dev;
|
|
|
|
dev_set_drvdata(priv->dev, priv);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2009-12-14 21:19:44 +00:00
|
|
|
priv->vbase = ioremap(res.start, resource_size(&res));
|
2008-02-06 21:36:21 +00:00
|
|
|
if (!priv->vbase) {
|
2010-10-18 07:22:31 +00:00
|
|
|
dev_err(dev, "failed to map chip region\n");
|
2008-02-06 21:36:21 +00:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2008-07-30 04:27:14 +00:00
|
|
|
priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
|
[MTD] [NAND] fsl_elbc_nand: fix mtd name
Currently fsl_elbc_nand doesn't initialize mtd->name, and this causes
nand_get_flash_type() to assign name that is equal to chip type, like
this:
root@b1:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00800000 00010000 "fe000000.flash"
mtd1: 02000000 00004000 "NAND 32MiB 3,3V 8-bit"
mtd0 is physmap_of flash (normal name), and mtd1 is fsl_elbc_nand.
Despite inconsistency, with mtd name like this specifying paritions
from the kernel command line becomes a torture (though, I didn't tried
and not sure if mtdparts= can handle spaces at all). Plus, this causes
real bugs when multiple fsl_elbc_nand chips registered.
With this patch applied fsl_elbc_nand chip will have proper name:
root@b1:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00800000 00010000 "fe000000.flash"
mtd1: 02000000 00004000 "e0600000.flash"
p.s. We can't use priv->dev->bus_id as in physmap_of, because
fsl_elbc_nand pretends to be a localbus controller, so its bus_id is
"address.localbus", which is incorrect and thus will also not work
for multiple chips.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2008-03-18 16:34:03 +00:00
|
|
|
if (!priv->mtd.name) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2008-02-06 21:36:21 +00:00
|
|
|
ret = fsl_elbc_chip_init(priv);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
2010-02-26 18:32:56 +00:00
|
|
|
ret = nand_scan_ident(&priv->mtd, 1, NULL);
|
2008-02-06 21:36:21 +00:00
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = fsl_elbc_chip_init_tail(&priv->mtd);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = nand_scan_tail(&priv->mtd);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/* First look for RedBoot table or partitions on the command
|
|
|
|
* line, these take precedence over device tree information */
|
2011-06-02 14:00:36 +00:00
|
|
|
mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
|
|
|
|
NULL, 0);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
2009-01-21 13:16:28 +00:00
|
|
|
printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
|
|
|
|
(unsigned long long)res.start, priv->bank);
|
2008-02-06 21:36:21 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
fsl_elbc_chip_remove(priv);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
static int fsl_elbc_nand_remove(struct platform_device *pdev)
|
2008-02-06 21:36:21 +00:00
|
|
|
{
|
2010-10-18 07:22:31 +00:00
|
|
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
|
2012-06-06 23:36:39 +00:00
|
|
|
struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
|
|
|
|
|
|
|
|
fsl_elbc_chip_remove(priv);
|
2010-10-18 07:22:31 +00:00
|
|
|
|
|
|
|
mutex_lock(&fsl_elbc_nand_mutex);
|
|
|
|
elbc_fcm_ctrl->counter--;
|
|
|
|
if (!elbc_fcm_ctrl->counter) {
|
|
|
|
fsl_lbc_ctrl_dev->nand = NULL;
|
|
|
|
kfree(elbc_fcm_ctrl);
|
2008-02-06 21:36:21 +00:00
|
|
|
}
|
2010-10-18 07:22:31 +00:00
|
|
|
mutex_unlock(&fsl_elbc_nand_mutex);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
static const struct of_device_id fsl_elbc_nand_match[] = {
|
|
|
|
{ .compatible = "fsl,elbc-fcm-nand", },
|
2008-02-06 21:36:21 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2010-10-18 07:22:31 +00:00
|
|
|
static struct platform_driver fsl_elbc_nand_driver = {
|
2008-02-06 21:36:21 +00:00
|
|
|
.driver = {
|
2010-10-18 07:22:31 +00:00
|
|
|
.name = "fsl,elbc-fcm-nand",
|
2010-04-13 23:13:02 +00:00
|
|
|
.owner = THIS_MODULE,
|
2010-10-18 07:22:31 +00:00
|
|
|
.of_match_table = fsl_elbc_nand_match,
|
2008-02-06 21:36:21 +00:00
|
|
|
},
|
2010-10-18 07:22:31 +00:00
|
|
|
.probe = fsl_elbc_nand_probe,
|
|
|
|
.remove = fsl_elbc_nand_remove,
|
2008-02-06 21:36:21 +00:00
|
|
|
};
|
|
|
|
|
2011-11-27 12:45:03 +00:00
|
|
|
module_platform_driver(fsl_elbc_nand_driver);
|
2008-02-06 21:36:21 +00:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Freescale");
|
|
|
|
MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
|