2005-04-16 22:20:36 +00:00
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/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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* Copyright (c) 2003, 2004 Maciej W. Rozycki
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*
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* Common time service routines for MIPS machines. See
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* Documentation/mips/time.README.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/param.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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2005-07-13 11:48:45 +00:00
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#include <asm/cache.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/compiler.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/div64.h>
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#include <asm/sections.h>
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#include <asm/time.h>
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/*
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* The integer part of the number of usecs per jiffy is taken from tick,
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* but the fractional part is not recorded, so we calculate it using the
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* initial value of HZ. This aids systems where tick isn't really an
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* integer (e.g. for HZ = 128).
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*/
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#define USECS_PER_JIFFY TICK_SIZE
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#define USECS_PER_JIFFY_FRAC ((unsigned long)(u32)((1000000ULL << 32) / HZ))
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#define TICK_SIZE (tick_nsec / 1000)
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/*
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* forward reference
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*/
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DEFINE_SPINLOCK(rtc_lock);
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/*
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* By default we provide the null RTC ops
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*/
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static unsigned long null_rtc_get_time(void)
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{
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return mktime(2000, 1, 1, 0, 0, 0);
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}
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static int null_rtc_set_time(unsigned long sec)
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{
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return 0;
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}
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2006-03-27 09:16:33 +00:00
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unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time;
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int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time;
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int (*rtc_mips_set_mmss)(unsigned long);
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2005-04-16 22:20:36 +00:00
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/* usecs per counter cycle, shifted to left by 32 bits */
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static unsigned int sll32_usecs_per_cycle;
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/* how many counter cycles in a jiffy */
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2005-07-13 11:48:45 +00:00
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static unsigned long cycles_per_jiffy __read_mostly;
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2005-04-16 22:20:36 +00:00
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/* Cycle counter value at the previous timer interrupt.. */
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static unsigned int timerhi, timerlo;
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/* expirelo is the count value for next CPU timer interrupt */
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static unsigned int expirelo;
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/*
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* Null timer ack for systems not needing one (e.g. i8254).
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*/
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static void null_timer_ack(void) { /* nothing */ }
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/*
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* Null high precision timer functions for systems lacking one.
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*/
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static unsigned int null_hpt_read(void)
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{
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return 0;
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}
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2005-07-13 11:48:45 +00:00
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static void null_hpt_init(unsigned int count)
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{
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/* nothing */
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}
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2005-04-16 22:20:36 +00:00
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/*
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* Timer ack for an R4k-compatible timer of a known frequency.
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*/
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static void c0_timer_ack(void)
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{
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unsigned int count;
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2005-07-14 17:47:57 +00:00
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#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */
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2005-04-16 22:20:36 +00:00
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/* Ack this timer interrupt and set the next one. */
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expirelo += cycles_per_jiffy;
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2005-07-14 17:47:57 +00:00
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#endif
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2005-04-16 22:20:36 +00:00
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write_c0_compare(expirelo);
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/* Check to see if we have missed any timer interrupts. */
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2006-04-05 08:45:45 +00:00
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while (((count = read_c0_count()) - expirelo) < 0x7fffffff) {
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2005-04-16 22:20:36 +00:00
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/* missed_timer_count++; */
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expirelo = count + cycles_per_jiffy;
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write_c0_compare(expirelo);
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}
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}
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/*
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* High precision timer functions for a R4k-compatible timer.
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*/
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static unsigned int c0_hpt_read(void)
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{
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return read_c0_count();
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}
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/* For use solely as a high precision timer. */
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static void c0_hpt_init(unsigned int count)
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{
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write_c0_count(read_c0_count() - count);
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}
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/* For use both as a high precision timer and an interrupt source. */
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static void c0_hpt_timer_init(unsigned int count)
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{
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count = read_c0_count() - count;
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expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
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write_c0_count(expirelo - cycles_per_jiffy);
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write_c0_compare(expirelo);
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write_c0_count(count);
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}
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int (*mips_timer_state)(void);
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void (*mips_timer_ack)(void);
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unsigned int (*mips_hpt_read)(void);
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void (*mips_hpt_init)(unsigned int);
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/*
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* Gettimeoffset routines. These routines returns the time duration
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* since last timer interrupt in usecs.
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*
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* If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset.
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* Otherwise use calibrate_gettimeoffset()
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*
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* If the CPU does not have the counter register, you can either supply
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* your own gettimeoffset() routine, or use null_gettimeoffset(), which
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* gives the same resolution as HZ.
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*/
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static unsigned long null_gettimeoffset(void)
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{
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return 0;
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}
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/* The function pointer to one of the gettimeoffset funcs. */
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unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset;
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static unsigned long fixed_rate_gettimeoffset(void)
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{
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u32 count;
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unsigned long res;
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (sll32_usecs_per_cycle)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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}
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/*
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* Cached "1/(clocks per usec) * 2^32" value.
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* It has to be recalculated once each jiffy.
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*/
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static unsigned long cached_quotient;
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/* Last jiffy when calibrate_divXX_gettimeoffset() was called. */
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static unsigned long last_jiffies;
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/*
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* This is moved from dec/time.c:do_ioasic_gettimeoffset() by Maciej.
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*/
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static unsigned long calibrate_div32_gettimeoffset(void)
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{
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u32 count;
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unsigned long res, tmp;
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unsigned long quotient;
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tmp = jiffies;
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quotient = cached_quotient;
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if (last_jiffies != tmp) {
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last_jiffies = tmp;
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if (last_jiffies != 0) {
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unsigned long r0;
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do_div64_32(r0, timerhi, timerlo, tmp);
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do_div64_32(quotient, USECS_PER_JIFFY,
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USECS_PER_JIFFY_FRAC, r0);
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cached_quotient = quotient;
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}
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}
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (quotient)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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}
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static unsigned long calibrate_div64_gettimeoffset(void)
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{
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u32 count;
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unsigned long res, tmp;
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unsigned long quotient;
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tmp = jiffies;
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quotient = cached_quotient;
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if (last_jiffies != tmp) {
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last_jiffies = tmp;
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if (last_jiffies) {
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unsigned long r0;
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__asm__(".set push\n\t"
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".set mips3\n\t"
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"lwu %0,%3\n\t"
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"dsll32 %1,%2,0\n\t"
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"or %1,%1,%0\n\t"
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"ddivu $0,%1,%4\n\t"
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"mflo %1\n\t"
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"dsll32 %0,%5,0\n\t"
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"or %0,%0,%6\n\t"
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"ddivu $0,%0,%1\n\t"
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"mflo %0\n\t"
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".set pop"
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: "=&r" (quotient), "=&r" (r0)
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: "r" (timerhi), "m" (timerlo),
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"r" (tmp), "r" (USECS_PER_JIFFY),
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"r" (USECS_PER_JIFFY_FRAC)
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: "hi", "lo", GCC_REG_ACCUM);
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cached_quotient = quotient;
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}
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}
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (quotient)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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}
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/* last time when xtime and rtc are sync'ed up */
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static long last_rtc_update;
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/*
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* local_timer_interrupt() does profiling and process accounting
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* on a per-CPU basis.
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*
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* In UP mode, it is invoked from the (global) timer_interrupt.
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*
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* In SMP mode, it might invoked by per-CPU timer interrupt, or
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* a broadcasted inter-processor interrupt which itself is triggered
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* by the global timer interrupt.
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*/
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void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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if (current->pid)
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profile_tick(CPU_PROFILING, regs);
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update_process_times(user_mode(regs));
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}
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/*
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* High-level timer interrupt service routines. This function
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* is set as irqaction->handler and is invoked through do_IRQ.
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*/
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irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned long j;
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unsigned int count;
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2006-03-14 23:46:58 +00:00
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write_seqlock(&xtime_lock);
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2005-04-16 22:20:36 +00:00
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count = mips_hpt_read();
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mips_timer_ack();
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/* Update timerhi/timerlo for intra-jiffy calibration. */
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timerhi += count < timerlo; /* Wrap around */
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timerlo = count;
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/*
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* call the generic timer interrupt handling
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*/
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2006-09-29 09:00:32 +00:00
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do_timer(1);
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2005-04-16 22:20:36 +00:00
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/*
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* If we have an externally synchronized Linux clock, then update
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2006-03-27 09:16:33 +00:00
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* CMOS clock accordingly every ~11 minutes. rtc_mips_set_time() has to be
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2005-04-16 22:20:36 +00:00
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* called as close as possible to 500 ms before the new second starts.
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*/
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2005-09-06 22:17:46 +00:00
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if (ntp_synced() &&
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2005-04-16 22:20:36 +00:00
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xtime.tv_sec > last_rtc_update + 660 &&
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(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
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(xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
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2006-03-27 09:16:33 +00:00
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if (rtc_mips_set_mmss(xtime.tv_sec) == 0) {
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2005-04-16 22:20:36 +00:00
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last_rtc_update = xtime.tv_sec;
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} else {
|
|
|
|
/* do it again in 60 s */
|
|
|
|
last_rtc_update = xtime.tv_sec - 600;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If jiffies has overflown in this timer_interrupt, we must
|
|
|
|
* update the timer[hi]/[lo] to make fast gettimeoffset funcs
|
|
|
|
* quotient calc still valid. -arca
|
|
|
|
*
|
|
|
|
* The first timer interrupt comes late as interrupts are
|
|
|
|
* enabled long after timers are initialized. Therefore the
|
|
|
|
* high precision timer is fast, leading to wrong gettimeoffset()
|
|
|
|
* calculations. We deal with it by setting it based on the
|
|
|
|
* number of its ticks between the second and the third interrupt.
|
|
|
|
* That is still somewhat imprecise, but it's a good estimate.
|
|
|
|
* --macro
|
|
|
|
*/
|
|
|
|
j = jiffies;
|
|
|
|
if (j < 4) {
|
|
|
|
static unsigned int prev_count;
|
|
|
|
static int hpt_initialized;
|
|
|
|
|
|
|
|
switch (j) {
|
|
|
|
case 0:
|
|
|
|
timerhi = timerlo = 0;
|
|
|
|
mips_hpt_init(count);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
prev_count = count;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
if (!hpt_initialized) {
|
|
|
|
unsigned int c3 = 3 * (count - prev_count);
|
|
|
|
|
|
|
|
timerhi = 0;
|
|
|
|
timerlo = c3;
|
|
|
|
mips_hpt_init(count - c3);
|
|
|
|
hpt_initialized = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-14 23:46:58 +00:00
|
|
|
write_sequnlock(&xtime_lock);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* In UP mode, we call local_timer_interrupt() to do profiling
|
|
|
|
* and process accouting.
|
|
|
|
*
|
|
|
|
* In SMP mode, local_timer_interrupt() is invoked by appropriate
|
|
|
|
* low-level local timer interrupt handler.
|
|
|
|
*/
|
|
|
|
local_timer_interrupt(irq, dev_id, regs);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2005-12-09 12:29:38 +00:00
|
|
|
int null_perf_irq(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int (*perf_irq)(struct pt_regs *regs) = null_perf_irq;
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(null_perf_irq);
|
|
|
|
EXPORT_SYMBOL(perf_irq);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
|
|
|
|
{
|
2005-12-09 12:29:38 +00:00
|
|
|
int r2 = cpu_has_mips_r2;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
irq_enter();
|
|
|
|
kstat_this_cpu.irqs[irq]++;
|
|
|
|
|
2005-12-09 12:29:38 +00:00
|
|
|
/*
|
|
|
|
* Suckage alert:
|
|
|
|
* Before R2 of the architecture there was no way to see if a
|
|
|
|
* performance counter interrupt was pending, so we have to run the
|
|
|
|
* performance counter interrupt handler anyway.
|
|
|
|
*/
|
|
|
|
if (!r2 || (read_c0_cause() & (1 << 26)))
|
|
|
|
if (perf_irq(regs))
|
|
|
|
goto out;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* we keep interrupt disabled all the time */
|
2005-12-09 12:29:38 +00:00
|
|
|
if (!r2 || (read_c0_cause() & (1 << 30)))
|
|
|
|
timer_interrupt(irq, NULL, regs);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-12-09 12:29:38 +00:00
|
|
|
out:
|
2005-04-16 22:20:36 +00:00
|
|
|
irq_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
irq_enter();
|
|
|
|
if (smp_processor_id() != 0)
|
|
|
|
kstat_this_cpu.irqs[irq]++;
|
|
|
|
|
|
|
|
/* we keep interrupt disabled all the time */
|
|
|
|
local_timer_interrupt(irq, NULL, regs);
|
|
|
|
|
|
|
|
irq_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* time_init() - it does the following things.
|
|
|
|
*
|
|
|
|
* 1) board_time_init() -
|
|
|
|
* a) (optional) set up RTC routines,
|
|
|
|
* b) (optional) calibrate and set the mips_hpt_frequency
|
|
|
|
* (only needed if you intended to use fixed_rate_gettimeoffset
|
|
|
|
* or use cpu counter as timer interrupt source)
|
2006-03-27 09:16:33 +00:00
|
|
|
* 2) setup xtime based on rtc_mips_get_time().
|
2005-04-16 22:20:36 +00:00
|
|
|
* 3) choose a appropriate gettimeoffset routine.
|
|
|
|
* 4) calculate a couple of cached variables for later usage
|
2006-07-09 20:38:56 +00:00
|
|
|
* 5) plat_timer_setup() -
|
2005-04-16 22:20:36 +00:00
|
|
|
* a) (optional) over-write any choices made above by time_init().
|
|
|
|
* b) machine specific code should setup the timer irqaction.
|
|
|
|
* c) enable the timer interrupt
|
|
|
|
*/
|
|
|
|
|
|
|
|
void (*board_time_init)(void);
|
|
|
|
|
|
|
|
unsigned int mips_hpt_frequency;
|
|
|
|
|
|
|
|
static struct irqaction timer_irqaction = {
|
|
|
|
.handler = timer_interrupt,
|
2006-07-02 02:29:20 +00:00
|
|
|
.flags = IRQF_DISABLED,
|
2005-04-16 22:20:36 +00:00
|
|
|
.name = "timer",
|
|
|
|
};
|
|
|
|
|
|
|
|
static unsigned int __init calibrate_hpt(void)
|
|
|
|
{
|
|
|
|
u64 frequency;
|
|
|
|
u32 hpt_start, hpt_end, hpt_count, hz;
|
|
|
|
|
|
|
|
const int loops = HZ / 10;
|
|
|
|
int log_2_loops = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We want to calibrate for 0.1s, but to avoid a 64-bit
|
|
|
|
* division we round the number of loops up to the nearest
|
|
|
|
* power of 2.
|
|
|
|
*/
|
|
|
|
while (loops > 1 << log_2_loops)
|
|
|
|
log_2_loops++;
|
|
|
|
i = 1 << log_2_loops;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for a rising edge of the timer interrupt.
|
|
|
|
*/
|
|
|
|
while (mips_timer_state());
|
|
|
|
while (!mips_timer_state());
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now see how many high precision timer ticks happen
|
|
|
|
* during the calculated number of periods between timer
|
|
|
|
* interrupts.
|
|
|
|
*/
|
|
|
|
hpt_start = mips_hpt_read();
|
|
|
|
do {
|
|
|
|
while (mips_timer_state());
|
|
|
|
while (!mips_timer_state());
|
|
|
|
} while (--i);
|
|
|
|
hpt_end = mips_hpt_read();
|
|
|
|
|
|
|
|
hpt_count = hpt_end - hpt_start;
|
|
|
|
hz = HZ;
|
|
|
|
frequency = (u64)hpt_count * (u64)hz;
|
|
|
|
|
|
|
|
return frequency >> log_2_loops;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init time_init(void)
|
|
|
|
{
|
|
|
|
if (board_time_init)
|
|
|
|
board_time_init();
|
|
|
|
|
2006-03-27 09:16:33 +00:00
|
|
|
if (!rtc_mips_set_mmss)
|
|
|
|
rtc_mips_set_mmss = rtc_mips_set_time;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-03-27 09:16:33 +00:00
|
|
|
xtime.tv_sec = rtc_mips_get_time();
|
2005-04-16 22:20:36 +00:00
|
|
|
xtime.tv_nsec = 0;
|
|
|
|
|
|
|
|
set_normalized_timespec(&wall_to_monotonic,
|
|
|
|
-xtime.tv_sec, -xtime.tv_nsec);
|
|
|
|
|
|
|
|
/* Choose appropriate high precision timer routines. */
|
|
|
|
if (!cpu_has_counter && !mips_hpt_read) {
|
|
|
|
/* No high precision timer -- sorry. */
|
|
|
|
mips_hpt_read = null_hpt_read;
|
|
|
|
mips_hpt_init = null_hpt_init;
|
|
|
|
} else if (!mips_hpt_frequency && !mips_timer_state) {
|
|
|
|
/* A high precision timer of unknown frequency. */
|
|
|
|
if (!mips_hpt_read) {
|
|
|
|
/* No external high precision timer -- use R4k. */
|
|
|
|
mips_hpt_read = c0_hpt_read;
|
|
|
|
mips_hpt_init = c0_hpt_init;
|
|
|
|
}
|
|
|
|
|
2005-12-08 14:04:24 +00:00
|
|
|
if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
|
|
|
|
(current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
|
|
|
|
(current_cpu_data.isa_level == MIPS_CPU_ISA_II))
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* We need to calibrate the counter but we don't have
|
|
|
|
* 64-bit division.
|
|
|
|
*/
|
|
|
|
do_gettimeoffset = calibrate_div32_gettimeoffset;
|
|
|
|
else
|
|
|
|
/*
|
|
|
|
* We need to calibrate the counter but we *do* have
|
|
|
|
* 64-bit division.
|
|
|
|
*/
|
|
|
|
do_gettimeoffset = calibrate_div64_gettimeoffset;
|
|
|
|
} else {
|
|
|
|
/* We know counter frequency. Or we can get it. */
|
|
|
|
if (!mips_hpt_read) {
|
|
|
|
/* No external high precision timer -- use R4k. */
|
|
|
|
mips_hpt_read = c0_hpt_read;
|
|
|
|
|
|
|
|
if (mips_timer_state)
|
|
|
|
mips_hpt_init = c0_hpt_init;
|
|
|
|
else {
|
|
|
|
/* No external timer interrupt -- use R4k. */
|
|
|
|
mips_hpt_init = c0_hpt_timer_init;
|
|
|
|
mips_timer_ack = c0_timer_ack;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!mips_hpt_frequency)
|
|
|
|
mips_hpt_frequency = calibrate_hpt();
|
|
|
|
|
|
|
|
do_gettimeoffset = fixed_rate_gettimeoffset;
|
|
|
|
|
|
|
|
/* Calculate cache parameters. */
|
|
|
|
cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
|
|
|
|
|
|
|
|
/* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq */
|
|
|
|
do_div64_32(sll32_usecs_per_cycle,
|
|
|
|
1000000, mips_hpt_frequency / 2,
|
|
|
|
mips_hpt_frequency);
|
|
|
|
|
|
|
|
/* Report the high precision timer rate for a reference. */
|
|
|
|
printk("Using %u.%03u MHz high precision timer.\n",
|
|
|
|
((mips_hpt_frequency + 500) / 1000) / 1000,
|
|
|
|
((mips_hpt_frequency + 500) / 1000) % 1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!mips_timer_ack)
|
|
|
|
/* No timer interrupt ack (e.g. i8254). */
|
|
|
|
mips_timer_ack = null_timer_ack;
|
|
|
|
|
|
|
|
/* This sets up the high precision timer for the first interrupt. */
|
|
|
|
mips_hpt_init(mips_hpt_read());
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Call board specific timer interrupt setup.
|
|
|
|
*
|
|
|
|
* this pointer must be setup in machine setup routine.
|
|
|
|
*
|
|
|
|
* Even if a machine chooses to use a low-level timer interrupt,
|
|
|
|
* it still needs to setup the timer_irqaction.
|
|
|
|
* In that case, it might be better to set timer_irqaction.handler
|
|
|
|
* to be NULL function so that we are sure the high-level code
|
|
|
|
* is not invoked accidentally.
|
|
|
|
*/
|
2006-07-09 20:38:56 +00:00
|
|
|
plat_timer_setup(&timer_irqaction);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define FEBRUARY 2
|
|
|
|
#define STARTOFTIME 1970
|
|
|
|
#define SECDAY 86400L
|
|
|
|
#define SECYR (SECDAY * 365)
|
|
|
|
#define leapyear(y) ((!((y) % 4) && ((y) % 100)) || !((y) % 400))
|
|
|
|
#define days_in_year(y) (leapyear(y) ? 366 : 365)
|
|
|
|
#define days_in_month(m) (month_days[(m) - 1])
|
|
|
|
|
|
|
|
static int month_days[12] = {
|
|
|
|
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
|
|
|
|
};
|
|
|
|
|
|
|
|
void to_tm(unsigned long tim, struct rtc_time *tm)
|
|
|
|
{
|
|
|
|
long hms, day, gday;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
gday = day = tim / SECDAY;
|
|
|
|
hms = tim % SECDAY;
|
|
|
|
|
|
|
|
/* Hours, minutes, seconds are easy */
|
|
|
|
tm->tm_hour = hms / 3600;
|
|
|
|
tm->tm_min = (hms % 3600) / 60;
|
|
|
|
tm->tm_sec = (hms % 3600) % 60;
|
|
|
|
|
|
|
|
/* Number of years in days */
|
|
|
|
for (i = STARTOFTIME; day >= days_in_year(i); i++)
|
|
|
|
day -= days_in_year(i);
|
|
|
|
tm->tm_year = i;
|
|
|
|
|
|
|
|
/* Number of months in days left */
|
|
|
|
if (leapyear(tm->tm_year))
|
|
|
|
days_in_month(FEBRUARY) = 29;
|
|
|
|
for (i = 1; day >= days_in_month(i); i++)
|
|
|
|
day -= days_in_month(i);
|
|
|
|
days_in_month(FEBRUARY) = 28;
|
|
|
|
tm->tm_mon = i - 1; /* tm_mon starts from 0 to 11 */
|
|
|
|
|
|
|
|
/* Days are what is left over (+1) from all that. */
|
|
|
|
tm->tm_mday = day + 1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Determine the day of week
|
|
|
|
*/
|
|
|
|
tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(rtc_lock);
|
|
|
|
EXPORT_SYMBOL(to_tm);
|
2006-03-27 09:16:33 +00:00
|
|
|
EXPORT_SYMBOL(rtc_mips_set_time);
|
|
|
|
EXPORT_SYMBOL(rtc_mips_get_time);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
unsigned long long sched_clock(void)
|
|
|
|
{
|
|
|
|
return (unsigned long long)jiffies*(1000000000/HZ);
|
|
|
|
}
|