2005-04-16 22:20:36 +00:00
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#
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# Cryptographic API
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#
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2008-03-30 08:36:09 +00:00
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obj-$(CONFIG_CRYPTO) += crypto.o
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crypto-objs := api.o cipher.o digest.o compress.o
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2005-04-16 22:20:36 +00:00
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2006-08-21 11:08:13 +00:00
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crypto_algapi-$(CONFIG_PROC_FS) += proc.o
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2007-08-29 08:06:15 +00:00
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crypto_algapi-objs := algapi.o scatterwalk.o $(crypto_algapi-y)
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2006-08-21 11:08:13 +00:00
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obj-$(CONFIG_CRYPTO_ALGAPI) += crypto_algapi.o
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2005-04-16 22:20:36 +00:00
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2007-08-30 07:36:14 +00:00
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obj-$(CONFIG_CRYPTO_AEAD) += aead.o
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2007-11-27 11:48:27 +00:00
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crypto_blkcipher-objs := ablkcipher.o
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crypto_blkcipher-objs += blkcipher.o
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2008-02-23 03:12:06 +00:00
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crypto_blkcipher-objs += chainiv.o
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crypto_blkcipher-objs += eseqiv.o
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2007-11-27 11:48:27 +00:00
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obj-$(CONFIG_CRYPTO_BLKCIPHER) += crypto_blkcipher.o
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2007-11-30 10:38:37 +00:00
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obj-$(CONFIG_CRYPTO_SEQIV) += seqiv.o
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2006-08-21 14:07:53 +00:00
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2006-08-19 12:24:23 +00:00
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crypto_hash-objs := hash.o
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obj-$(CONFIG_CRYPTO_HASH) += crypto_hash.o
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2006-09-21 01:31:44 +00:00
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obj-$(CONFIG_CRYPTO_MANAGER) += cryptomgr.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_HMAC) += hmac.o
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2006-10-28 03:15:24 +00:00
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obj-$(CONFIG_CRYPTO_XCBC) += xcbc.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_NULL) += crypto_null.o
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obj-$(CONFIG_CRYPTO_MD4) += md4.o
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obj-$(CONFIG_CRYPTO_MD5) += md5.o
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2007-10-08 03:45:10 +00:00
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obj-$(CONFIG_CRYPTO_SHA1) += sha1_generic.o
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obj-$(CONFIG_CRYPTO_SHA256) += sha256_generic.o
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2008-03-06 11:55:38 +00:00
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obj-$(CONFIG_CRYPTO_SHA512) += sha512_generic.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_WP512) += wp512.o
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obj-$(CONFIG_CRYPTO_TGR192) += tgr192.o
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2006-11-29 07:59:44 +00:00
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obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o
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2006-09-21 01:44:08 +00:00
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obj-$(CONFIG_CRYPTO_ECB) += ecb.o
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obj-$(CONFIG_CRYPTO_CBC) += cbc.o
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2006-12-16 01:09:02 +00:00
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obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o
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2008-03-24 13:26:16 +00:00
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obj-$(CONFIG_CRYPTO_CTS) += cts.o
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2006-11-25 22:43:10 +00:00
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obj-$(CONFIG_CRYPTO_LRW) += lrw.o
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2007-09-19 12:23:13 +00:00
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obj-$(CONFIG_CRYPTO_XTS) += xts.o
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[CRYPTO] ctr: Add CTR (Counter) block cipher mode
This patch implements CTR mode for IPsec.
It is based off of RFC 3686.
Please note:
1. CTR turns a block cipher into a stream cipher.
Encryption is done in blocks, however the last block
may be a partial block.
A "counter block" is encrypted, creating a keystream
that is xor'ed with the plaintext. The counter portion
of the counter block is incremented after each block
of plaintext is encrypted.
Decryption is performed in same manner.
2. The CTR counterblock is composed of,
nonce + IV + counter
The size of the counterblock is equivalent to the
blocksize of the cipher.
sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize
The CTR template requires the name of the cipher
algorithm, the sizeof the nonce, and the sizeof the iv.
ctr(cipher,sizeof_nonce,sizeof_iv)
So for example,
ctr(aes,4,8)
specifies the counterblock will be composed of 4 bytes
from a nonce, 8 bytes from the iv, and 4 bytes for counter
since aes has a blocksize of 16 bytes.
3. The counter portion of the counter block is stored
in big endian for conformance to rfc 3686.
Signed-off-by: Joy Latten <latten@austin.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-23 00:50:32 +00:00
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obj-$(CONFIG_CRYPTO_CTR) += ctr.o
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2007-11-26 14:24:11 +00:00
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obj-$(CONFIG_CRYPTO_GCM) += gcm.o
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2007-12-12 12:25:13 +00:00
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obj-$(CONFIG_CRYPTO_CCM) += ccm.o
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2007-04-16 10:49:20 +00:00
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obj-$(CONFIG_CRYPTO_CRYPTD) += cryptd.o
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2007-10-05 08:42:03 +00:00
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obj-$(CONFIG_CRYPTO_DES) += des_generic.o
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2006-12-16 01:13:14 +00:00
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obj-$(CONFIG_CRYPTO_FCRYPT) += fcrypt.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_BLOWFISH) += blowfish.o
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obj-$(CONFIG_CRYPTO_TWOFISH) += twofish.o
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2006-06-20 10:37:23 +00:00
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obj-$(CONFIG_CRYPTO_TWOFISH_COMMON) += twofish_common.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_SERPENT) += serpent.o
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2007-10-05 08:52:01 +00:00
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obj-$(CONFIG_CRYPTO_AES) += aes_generic.o
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2007-01-24 10:47:48 +00:00
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obj-$(CONFIG_CRYPTO_CAMELLIA) += camellia.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_CAST5) += cast5.o
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obj-$(CONFIG_CRYPTO_CAST6) += cast6.o
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obj-$(CONFIG_CRYPTO_ARC4) += arc4.o
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obj-$(CONFIG_CRYPTO_TEA) += tea.o
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obj-$(CONFIG_CRYPTO_KHAZAD) += khazad.o
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obj-$(CONFIG_CRYPTO_ANUBIS) += anubis.o
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2007-08-21 12:01:03 +00:00
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obj-$(CONFIG_CRYPTO_SEED) += seed.o
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2007-11-23 11:45:00 +00:00
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obj-$(CONFIG_CRYPTO_SALSA20) += salsa20_generic.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_DEFLATE) += deflate.o
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obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o
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obj-$(CONFIG_CRYPTO_CRC32C) += crc32c.o
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[CRYPTO] aead: Add authenc
This patch adds the authenc algorithm which constructs an AEAD algorithm
from an asynchronous block cipher and a hash. The construction is done
by concatenating the encrypted result from the cipher with the output
from the hash, as is used by the IPsec ESP protocol.
The authenc algorithm exists as a template with four parameters:
authenc(auth, authsize, enc, enckeylen).
The authentication algorithm, the authentication size (i.e., truncating
the output of the authentication algorithm), the encryption algorithm,
and the encryption key length. Both the size field and the key length
field are in bytes. For example, AES-128 with SHA1-HMAC would be
represented by
authenc(hmac(sha1), 12, cbc(aes), 16)
The key for the authenc algorithm is the concatenation of the keys for
the authentication algorithm with the encryption algorithm. For the
above example, if a key of length 36 bytes is given, then hmac(sha1)
would receive the first 20 bytes while the last 16 would be given to
cbc(aes).
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-08-30 08:24:15 +00:00
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obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o
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2007-12-07 08:53:23 +00:00
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obj-$(CONFIG_CRYPTO_LZO) += lzo.o
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2005-04-16 22:20:36 +00:00
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obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o
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2007-07-09 18:56:42 +00:00
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#
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# generic algorithms and the async_tx api
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#
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obj-$(CONFIG_XOR_BLOCKS) += xor.o
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async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 18:10:44 +00:00
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obj-$(CONFIG_ASYNC_CORE) += async_tx/
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