309 lines
8.4 KiB
C
309 lines
8.4 KiB
C
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* IT8172 IDE controller support
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/it8172/it8172_int.h>
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/*
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* Prototypes
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*/
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static u8 it8172_ratemask (ide_drive_t *drive)
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{
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return 1;
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}
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static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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int is_slave = (&hwif->drives[1] == drive);
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unsigned long flags;
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u16 drive_enables;
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u32 drive_timing;
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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spin_lock_irqsave(&ide_lock, flags);
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pci_read_config_word(dev, 0x40, &drive_enables);
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pci_read_config_dword(dev, 0x44, &drive_timing);
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/*
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* FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
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* are being left at the default values of 8 PCI clocks (242 nsec
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* for a 33 MHz clock). These can be safely shortened at higher
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* PIO modes. The DIOR/DIOW pulse width and recovery times only
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* apply to PIO modes, not to the DMA modes.
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*/
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/*
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* Enable port 0x44. The IT8172G spec is confused; it calls
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* this register the "Slave IDE Timing Register", but in fact,
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* it controls timing for both master and slave drives.
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*/
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drive_enables |= 0x4000;
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if (is_slave) {
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drive_enables &= 0xc006;
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if (pio > 1)
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/* enable prefetch and IORDY sample-point */
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drive_enables |= 0x0060;
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} else {
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drive_enables &= 0xc060;
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if (pio > 1)
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/* enable prefetch and IORDY sample-point */
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drive_enables |= 0x0006;
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}
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pci_write_config_word(dev, 0x40, drive_enables);
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spin_unlock_irqrestore(&ide_lock, flags);
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}
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static u8 it8172_dma_2_pio (u8 xfer_rate)
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{
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switch(xfer_rate) {
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case XFER_UDMA_5:
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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case XFER_MW_DMA_2:
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case XFER_PIO_4:
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return 4;
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case XFER_MW_DMA_1:
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case XFER_PIO_3:
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return 3;
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case XFER_SW_DMA_2:
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case XFER_PIO_2:
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return 2;
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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case XFER_PIO_1:
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case XFER_PIO_0:
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case XFER_PIO_SLOW:
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default:
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return 0;
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}
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}
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static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);
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int a_speed = 3 << (drive->dn * 4);
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int u_flag = 1 << drive->dn;
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int u_speed = 0;
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u8 reg48, reg4a;
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pci_read_config_byte(dev, 0x48, ®48);
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pci_read_config_byte(dev, 0x4a, ®4a);
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/*
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* Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
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* at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
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* transfers on some drives, even though both numbers meet the minimum
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* ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
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* So the faster times are just commented out here. The good news is
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* that the slower cycle time has very little affect on transfer
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* performance.
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*/
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switch(speed) {
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case XFER_UDMA_4:
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case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;
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case XFER_UDMA_5:
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case XFER_UDMA_3:
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case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;
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case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_2: break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_0: break;
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default: return -1;
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}
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if (speed >= XFER_UDMA_0) {
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pci_write_config_byte(dev, 0x48, reg48 | u_flag);
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reg4a &= ~a_speed;
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pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
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} else {
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pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
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pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
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}
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it8172_tune_drive(drive, it8172_dma_2_pio(speed));
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return (ide_config_drive_speed(drive, speed));
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}
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static int it8172_config_chipset_for_dma (ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
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if (!(speed)) {
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u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
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speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
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}
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(void) it8172_tune_chipset(drive, speed);
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return ide_dma_enable(drive);
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}
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static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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drive->init_speed = 0;
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if (id && (id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (it8172_config_chipset_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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it8172_tune_drive(drive, 5);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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static unsigned int __init init_chipset_it8172 (struct pci_dev *dev, const char *name)
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{
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unsigned char progif;
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/*
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* Place both IDE interfaces into PCI "native" mode
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*/
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pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
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pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
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return IT8172_IDE_IRQ;
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}
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static void __init init_hwif_it8172 (ide_hwif_t *hwif)
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{
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struct pci_dev* dev = hwif->pci_dev;
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unsigned long cmdBase, ctrlBase;
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hwif->autodma = 0;
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hwif->tuneproc = &it8172_tune_drive;
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hwif->speedproc = &it8172_tune_chipset;
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cmdBase = dev->resource[0].start;
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ctrlBase = dev->resource[1].start;
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ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
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memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
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hwif->noprobe = 0;
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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return;
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}
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x07;
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hwif->mwdma_mask = 0x06;
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hwif->swdma_mask = 0x04;
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hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static ide_pci_device_t it8172_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "IT8172G",
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.init_chipset = init_chipset_it8172,
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.init_hwif = init_hwif_it8172,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x40,0x00,0x01}},
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.bootable = ON_BOARD,
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}
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};
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static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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if ((!(PCI_FUNC(dev->devfn) & 1) ||
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(!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
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return -ENODEV; /* IT8172 is more than an IDE controller */
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return ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
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}
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static struct pci_device_id it8172_pci_tbl[] = {
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{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
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static struct pci_driver driver = {
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.name = "IT8172_IDE",
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.id_table = it8172_pci_tbl,
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.probe = it8172_init_one,
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};
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static int it8172_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(it8172_ide_init);
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MODULE_AUTHOR("SteveL@mvista.com");
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MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
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MODULE_LICENSE("GPL");
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