2011-09-21 09:30:18 +00:00
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/*
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* Performance events - AMD IBS
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/perf_event.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/apic.h>
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static u32 ibs_caps;
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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2011-12-15 16:56:37 +00:00
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#include <linux/kprobes.h>
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#include <linux/hardirq.h>
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#include <asm/nmi.h>
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2011-12-15 16:56:36 +00:00
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#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
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#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
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2011-12-15 16:56:38 +00:00
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enum ibs_states {
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IBS_ENABLED = 0,
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IBS_STARTED = 1,
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IBS_STOPPING = 2,
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IBS_MAX_STATES,
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};
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struct cpu_perf_ibs {
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struct perf_event *event;
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unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
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};
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2011-12-15 16:56:36 +00:00
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struct perf_ibs {
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struct pmu pmu;
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unsigned int msr;
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u64 config_mask;
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u64 cnt_mask;
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u64 enable_mask;
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2011-12-15 16:56:37 +00:00
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u64 valid_mask;
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2011-12-15 16:56:39 +00:00
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u64 max_period;
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2011-12-15 16:56:37 +00:00
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unsigned long offset_mask[1];
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int offset_max;
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2011-12-15 16:56:38 +00:00
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struct cpu_perf_ibs __percpu *pcpu;
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2011-12-15 16:56:39 +00:00
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u64 (*get_count)(u64 config);
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2011-12-15 16:56:37 +00:00
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};
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struct perf_ibs_data {
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u32 size;
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union {
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u32 data[0]; /* data buffer starts here */
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u32 caps;
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};
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u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
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2011-12-15 16:56:36 +00:00
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};
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2011-12-15 16:56:39 +00:00
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static int
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perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *count)
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{
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int overflow = 0;
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/*
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* If we are way outside a reasonable range then just skip forward:
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*/
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left < min))
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left = min;
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if (left > max)
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left = max;
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*count = (u64)left;
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return overflow;
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}
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static int
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perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
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{
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struct hw_perf_event *hwc = &event->hw;
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int shift = 64 - width;
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u64 prev_raw_count;
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u64 delta;
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/*
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* Careful: an NMI might modify the previous event value.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic event atomically:
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*/
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prev_raw_count = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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return 0;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (event-)time and add that to the generic event.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count.
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*/
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return 1;
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}
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2011-12-15 16:56:36 +00:00
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static struct perf_ibs perf_ibs_fetch;
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static struct perf_ibs perf_ibs_op;
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static struct perf_ibs *get_ibs_pmu(int type)
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{
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if (perf_ibs_fetch.pmu.type == type)
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return &perf_ibs_fetch;
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if (perf_ibs_op.pmu.type == type)
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return &perf_ibs_op;
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return NULL;
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}
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2011-09-21 09:30:18 +00:00
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static int perf_ibs_init(struct perf_event *event)
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{
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2011-12-15 16:56:36 +00:00
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs;
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u64 max_cnt, config;
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perf_ibs = get_ibs_pmu(event->attr.type);
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if (!perf_ibs)
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2011-09-21 09:30:18 +00:00
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return -ENOENT;
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2011-12-15 16:56:36 +00:00
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config = event->attr.config;
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if (config & ~perf_ibs->config_mask)
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return -EINVAL;
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if (hwc->sample_period) {
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if (config & perf_ibs->cnt_mask)
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/* raw max_cnt may not be set */
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return -EINVAL;
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if (hwc->sample_period & 0x0f)
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/* lower 4 bits can not be set in ibs max cnt */
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return -EINVAL;
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} else {
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max_cnt = config & perf_ibs->cnt_mask;
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2011-12-15 16:56:39 +00:00
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config &= ~perf_ibs->cnt_mask;
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2011-12-15 16:56:36 +00:00
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event->attr.sample_period = max_cnt << 4;
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hwc->sample_period = event->attr.sample_period;
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}
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2011-12-15 16:56:39 +00:00
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if (!hwc->sample_period)
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2011-12-15 16:56:36 +00:00
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return -EINVAL;
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hwc->config_base = perf_ibs->msr;
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hwc->config = config;
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2011-09-21 09:30:18 +00:00
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return 0;
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}
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2011-12-15 16:56:39 +00:00
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static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
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struct hw_perf_event *hwc, u64 *period)
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{
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int ret;
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/* ignore lower 4 bits in min count: */
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ret = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
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local64_set(&hwc->prev_count, 0);
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return ret;
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}
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static u64 get_ibs_fetch_count(u64 config)
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{
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return (config & IBS_FETCH_CNT) >> 12;
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}
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static u64 get_ibs_op_count(u64 config)
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{
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return (config & IBS_OP_CUR_CNT) >> 32;
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}
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static void
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perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
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u64 config)
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{
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u64 count = perf_ibs->get_count(config);
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while (!perf_event_try_update(event, count, 20)) {
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rdmsrl(event->hw.config_base, config);
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count = perf_ibs->get_count(config);
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}
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}
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/* Note: The enable mask must be encoded in the config argument. */
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static inline void perf_ibs_enable_event(struct hw_perf_event *hwc, u64 config)
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{
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wrmsrl(hwc->config_base, hwc->config | config);
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}
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/*
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* We cannot restore the ibs pmu state, so we always needs to update
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* the event while stopping it and then reset the state when starting
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* again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
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* perf_ibs_start()/perf_ibs_stop() and instead always do it.
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*/
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2011-12-15 16:56:38 +00:00
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static void perf_ibs_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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2011-12-15 16:56:39 +00:00
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u64 config;
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2011-12-15 16:56:38 +00:00
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2011-12-15 16:56:39 +00:00
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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2011-12-15 16:56:38 +00:00
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return;
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2011-12-15 16:56:39 +00:00
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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perf_ibs_set_period(perf_ibs, hwc, &config);
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config = (config >> 4) | perf_ibs->enable_mask;
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set_bit(IBS_STARTED, pcpu->state);
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perf_ibs_enable_event(hwc, config);
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perf_event_update_userpage(event);
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2011-12-15 16:56:38 +00:00
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}
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static void perf_ibs_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 val;
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2011-12-15 16:56:39 +00:00
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int stopping;
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2011-12-15 16:56:38 +00:00
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2011-12-15 16:56:39 +00:00
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stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
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2011-12-15 16:56:38 +00:00
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2011-12-15 16:56:39 +00:00
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if (!stopping && (hwc->state & PERF_HES_UPTODATE))
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return;
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2011-12-15 16:56:38 +00:00
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rdmsrl(hwc->config_base, val);
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2011-12-15 16:56:39 +00:00
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if (stopping) {
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set_bit(IBS_STOPPING, pcpu->state);
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val &= ~perf_ibs->enable_mask;
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wrmsrl(hwc->config_base, val);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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}
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_ibs_event_update(perf_ibs, event, val);
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hwc->state |= PERF_HES_UPTODATE;
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2011-12-15 16:56:38 +00:00
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}
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2011-09-21 09:30:18 +00:00
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static int perf_ibs_add(struct perf_event *event, int flags)
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{
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2011-12-15 16:56:38 +00:00
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (test_and_set_bit(IBS_ENABLED, pcpu->state))
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return -ENOSPC;
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2011-12-15 16:56:39 +00:00
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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2011-12-15 16:56:38 +00:00
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pcpu->event = event;
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if (flags & PERF_EF_START)
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perf_ibs_start(event, PERF_EF_RELOAD);
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2011-09-21 09:30:18 +00:00
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return 0;
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}
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static void perf_ibs_del(struct perf_event *event, int flags)
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{
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2011-12-15 16:56:38 +00:00
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
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return;
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2011-12-15 16:56:39 +00:00
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perf_ibs_stop(event, PERF_EF_UPDATE);
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2011-12-15 16:56:38 +00:00
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pcpu->event = NULL;
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2011-12-15 16:56:39 +00:00
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perf_event_update_userpage(event);
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2011-09-21 09:30:18 +00:00
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}
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2011-12-15 16:56:38 +00:00
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static void perf_ibs_read(struct perf_event *event) { }
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2011-12-15 16:56:36 +00:00
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static struct perf_ibs perf_ibs_fetch = {
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.pmu = {
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.task_ctx_nr = perf_invalid_context,
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.event_init = perf_ibs_init,
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.add = perf_ibs_add,
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.del = perf_ibs_del,
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2011-12-15 16:56:38 +00:00
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.start = perf_ibs_start,
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.stop = perf_ibs_stop,
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.read = perf_ibs_read,
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2011-12-15 16:56:36 +00:00
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},
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.msr = MSR_AMD64_IBSFETCHCTL,
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.config_mask = IBS_FETCH_CONFIG_MASK,
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.cnt_mask = IBS_FETCH_MAX_CNT,
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.enable_mask = IBS_FETCH_ENABLE,
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2011-12-15 16:56:37 +00:00
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.valid_mask = IBS_FETCH_VAL,
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2011-12-15 16:56:39 +00:00
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.max_period = IBS_FETCH_MAX_CNT << 4,
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2011-12-15 16:56:37 +00:00
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.offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
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.offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
|
2011-12-15 16:56:39 +00:00
|
|
|
|
|
|
|
.get_count = get_ibs_fetch_count,
|
2011-12-15 16:56:36 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct perf_ibs perf_ibs_op = {
|
|
|
|
.pmu = {
|
|
|
|
.task_ctx_nr = perf_invalid_context,
|
|
|
|
|
|
|
|
.event_init = perf_ibs_init,
|
|
|
|
.add = perf_ibs_add,
|
|
|
|
.del = perf_ibs_del,
|
2011-12-15 16:56:38 +00:00
|
|
|
.start = perf_ibs_start,
|
|
|
|
.stop = perf_ibs_stop,
|
|
|
|
.read = perf_ibs_read,
|
2011-12-15 16:56:36 +00:00
|
|
|
},
|
|
|
|
.msr = MSR_AMD64_IBSOPCTL,
|
|
|
|
.config_mask = IBS_OP_CONFIG_MASK,
|
|
|
|
.cnt_mask = IBS_OP_MAX_CNT,
|
|
|
|
.enable_mask = IBS_OP_ENABLE,
|
2011-12-15 16:56:37 +00:00
|
|
|
.valid_mask = IBS_OP_VAL,
|
2011-12-15 16:56:39 +00:00
|
|
|
.max_period = IBS_OP_MAX_CNT << 4,
|
2011-12-15 16:56:37 +00:00
|
|
|
.offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
|
|
|
|
.offset_max = MSR_AMD64_IBSOP_REG_COUNT,
|
2011-12-15 16:56:39 +00:00
|
|
|
|
|
|
|
.get_count = get_ibs_op_count,
|
2011-09-21 09:30:18 +00:00
|
|
|
};
|
|
|
|
|
2011-12-15 16:56:37 +00:00
|
|
|
static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
|
|
|
|
{
|
2011-12-15 16:56:38 +00:00
|
|
|
struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
|
|
|
|
struct perf_event *event = pcpu->event;
|
2011-12-15 16:56:37 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
struct perf_sample_data data;
|
|
|
|
struct perf_raw_record raw;
|
|
|
|
struct pt_regs regs;
|
|
|
|
struct perf_ibs_data ibs_data;
|
2011-12-15 16:56:39 +00:00
|
|
|
int offset, size, overflow, reenable;
|
2011-12-15 16:56:37 +00:00
|
|
|
unsigned int msr;
|
2011-12-15 16:56:39 +00:00
|
|
|
u64 *buf, config;
|
2011-12-15 16:56:37 +00:00
|
|
|
|
2011-12-15 16:56:38 +00:00
|
|
|
if (!test_bit(IBS_STARTED, pcpu->state)) {
|
|
|
|
/* Catch spurious interrupts after stopping IBS: */
|
|
|
|
if (!test_and_clear_bit(IBS_STOPPING, pcpu->state))
|
|
|
|
return 0;
|
|
|
|
rdmsrl(perf_ibs->msr, *ibs_data.regs);
|
|
|
|
return (*ibs_data.regs & perf_ibs->valid_mask) ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
2011-12-15 16:56:37 +00:00
|
|
|
msr = hwc->config_base;
|
|
|
|
buf = ibs_data.regs;
|
|
|
|
rdmsrl(msr, *buf);
|
|
|
|
if (!(*buf++ & perf_ibs->valid_mask))
|
|
|
|
return 0;
|
|
|
|
|
2012-04-02 18:19:07 +00:00
|
|
|
/*
|
|
|
|
* Emulate IbsOpCurCnt in MSRC001_1033 (IbsOpCtl), not
|
|
|
|
* supported in all cpus. As this triggered an interrupt, we
|
|
|
|
* set the current count to the max count.
|
|
|
|
*/
|
|
|
|
config = ibs_data.regs[0];
|
|
|
|
if (perf_ibs == &perf_ibs_op && !(ibs_caps & IBS_CAPS_RDWROPCNT)) {
|
|
|
|
config &= ~IBS_OP_CUR_CNT;
|
|
|
|
config |= (config & IBS_OP_MAX_CNT) << 36;
|
|
|
|
}
|
|
|
|
|
|
|
|
perf_ibs_event_update(perf_ibs, event, config);
|
2011-12-15 16:56:37 +00:00
|
|
|
perf_sample_data_init(&data, 0);
|
2012-04-02 18:19:07 +00:00
|
|
|
data.period = event->hw.last_period;
|
|
|
|
|
2011-12-15 16:56:37 +00:00
|
|
|
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
|
|
|
|
ibs_data.caps = ibs_caps;
|
|
|
|
size = 1;
|
|
|
|
offset = 1;
|
|
|
|
do {
|
|
|
|
rdmsrl(msr + offset, *buf++);
|
|
|
|
size++;
|
|
|
|
offset = find_next_bit(perf_ibs->offset_mask,
|
|
|
|
perf_ibs->offset_max,
|
|
|
|
offset + 1);
|
|
|
|
} while (offset < perf_ibs->offset_max);
|
|
|
|
raw.size = sizeof(u32) + sizeof(u64) * size;
|
|
|
|
raw.data = ibs_data.data;
|
|
|
|
data.raw = &raw;
|
|
|
|
}
|
|
|
|
|
|
|
|
regs = *iregs; /* XXX: update ip from ibs sample */
|
|
|
|
|
2011-12-15 16:56:39 +00:00
|
|
|
overflow = perf_ibs_set_period(perf_ibs, hwc, &config);
|
|
|
|
reenable = !(overflow && perf_event_overflow(event, &data, ®s));
|
|
|
|
config = (config >> 4) | (reenable ? perf_ibs->enable_mask : 0);
|
|
|
|
perf_ibs_enable_event(hwc, config);
|
|
|
|
|
|
|
|
perf_event_update_userpage(event);
|
2011-12-15 16:56:37 +00:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __kprobes
|
|
|
|
perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
int handled = 0;
|
|
|
|
|
|
|
|
handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
|
|
|
|
handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
|
|
|
|
|
|
|
|
if (handled)
|
|
|
|
inc_irq_stat(apic_perf_irqs);
|
|
|
|
|
|
|
|
return handled;
|
|
|
|
}
|
|
|
|
|
2011-12-15 16:56:38 +00:00
|
|
|
static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
|
|
|
|
{
|
|
|
|
struct cpu_perf_ibs __percpu *pcpu;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
pcpu = alloc_percpu(struct cpu_perf_ibs);
|
|
|
|
if (!pcpu)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
perf_ibs->pcpu = pcpu;
|
|
|
|
|
|
|
|
ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
|
|
|
|
if (ret) {
|
|
|
|
perf_ibs->pcpu = NULL;
|
|
|
|
free_percpu(pcpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-09-21 09:30:18 +00:00
|
|
|
static __init int perf_event_ibs_init(void)
|
|
|
|
{
|
|
|
|
if (!ibs_caps)
|
|
|
|
return -ENODEV; /* ibs not supported by the cpu */
|
|
|
|
|
2011-12-15 16:56:38 +00:00
|
|
|
perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
|
|
|
|
perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
|
2012-04-25 10:55:22 +00:00
|
|
|
register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
|
2011-09-21 09:30:18 +00:00
|
|
|
printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
|
|
|
|
|
|
|
|
static __init int perf_event_ibs_init(void) { return 0; }
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* IBS - apic initialization, for perf and oprofile */
|
|
|
|
|
|
|
|
static __init u32 __get_ibs_caps(void)
|
|
|
|
{
|
|
|
|
u32 caps;
|
|
|
|
unsigned int max_level;
|
|
|
|
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_IBS))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* check IBS cpuid feature flags */
|
|
|
|
max_level = cpuid_eax(0x80000000);
|
|
|
|
if (max_level < IBS_CPUID_FEATURES)
|
|
|
|
return IBS_CAPS_DEFAULT;
|
|
|
|
|
|
|
|
caps = cpuid_eax(IBS_CPUID_FEATURES);
|
|
|
|
if (!(caps & IBS_CAPS_AVAIL))
|
|
|
|
/* cpuid flags not valid */
|
|
|
|
return IBS_CAPS_DEFAULT;
|
|
|
|
|
|
|
|
return caps;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 get_ibs_caps(void)
|
|
|
|
{
|
|
|
|
return ibs_caps;
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(get_ibs_caps);
|
|
|
|
|
|
|
|
static inline int get_eilvt(int offset)
|
|
|
|
{
|
|
|
|
return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int put_eilvt(int offset)
|
|
|
|
{
|
|
|
|
return !setup_APIC_eilvt(offset, 0, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check and reserve APIC extended interrupt LVT offset for IBS if available.
|
|
|
|
*/
|
|
|
|
static inline int ibs_eilvt_valid(void)
|
|
|
|
{
|
|
|
|
int offset;
|
|
|
|
u64 val;
|
|
|
|
int valid = 0;
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
|
|
|
|
rdmsrl(MSR_AMD64_IBSCTL, val);
|
|
|
|
offset = val & IBSCTL_LVT_OFFSET_MASK;
|
|
|
|
|
|
|
|
if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
|
|
|
|
pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
|
|
|
|
smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!get_eilvt(offset)) {
|
|
|
|
pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
|
|
|
|
smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
valid = 1;
|
|
|
|
out:
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
return valid;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int setup_ibs_ctl(int ibs_eilvt_off)
|
|
|
|
{
|
|
|
|
struct pci_dev *cpu_cfg;
|
|
|
|
int nodes;
|
|
|
|
u32 value = 0;
|
|
|
|
|
|
|
|
nodes = 0;
|
|
|
|
cpu_cfg = NULL;
|
|
|
|
do {
|
|
|
|
cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
|
|
|
|
PCI_DEVICE_ID_AMD_10H_NB_MISC,
|
|
|
|
cpu_cfg);
|
|
|
|
if (!cpu_cfg)
|
|
|
|
break;
|
|
|
|
++nodes;
|
|
|
|
pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
|
|
|
|
| IBSCTL_LVT_OFFSET_VALID);
|
|
|
|
pci_read_config_dword(cpu_cfg, IBSCTL, &value);
|
|
|
|
if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
|
|
|
|
pci_dev_put(cpu_cfg);
|
|
|
|
printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
|
|
|
|
"IBSCTL = 0x%08x\n", value);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
} while (1);
|
|
|
|
|
|
|
|
if (!nodes) {
|
|
|
|
printk(KERN_DEBUG "No CPU node configured for IBS\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This runs only on the current cpu. We try to find an LVT offset and
|
|
|
|
* setup the local APIC. For this we must disable preemption. On
|
|
|
|
* success we initialize all nodes with this offset. This updates then
|
|
|
|
* the offset in the IBS_CTL per-node msr. The per-core APIC setup of
|
|
|
|
* the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
|
|
|
|
* is using the new offset.
|
|
|
|
*/
|
|
|
|
static int force_ibs_eilvt_setup(void)
|
|
|
|
{
|
|
|
|
int offset;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
/* find the next free available EILVT entry, skip offset 0 */
|
|
|
|
for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
|
|
|
|
if (get_eilvt(offset))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
if (offset == APIC_EILVT_NR_MAX) {
|
|
|
|
printk(KERN_DEBUG "No EILVT entry available\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = setup_ibs_ctl(offset);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (!ibs_eilvt_valid()) {
|
|
|
|
ret = -EFAULT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2011-11-08 18:20:44 +00:00
|
|
|
pr_info("IBS: LVT offset %d assigned\n", offset);
|
2011-09-21 09:30:18 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
out:
|
|
|
|
preempt_disable();
|
|
|
|
put_eilvt(offset);
|
|
|
|
preempt_enable();
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_ibs_lvt_offset(void)
|
|
|
|
{
|
|
|
|
u64 val;
|
|
|
|
|
|
|
|
rdmsrl(MSR_AMD64_IBSCTL, val);
|
|
|
|
if (!(val & IBSCTL_LVT_OFFSET_VALID))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return val & IBSCTL_LVT_OFFSET_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void setup_APIC_ibs(void *dummy)
|
|
|
|
{
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
offset = get_ibs_lvt_offset();
|
|
|
|
if (offset < 0)
|
|
|
|
goto failed;
|
|
|
|
|
|
|
|
if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
|
|
|
|
return;
|
|
|
|
failed:
|
|
|
|
pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
|
|
|
|
smp_processor_id());
|
|
|
|
}
|
|
|
|
|
|
|
|
static void clear_APIC_ibs(void *dummy)
|
|
|
|
{
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
offset = get_ibs_lvt_offset();
|
|
|
|
if (offset >= 0)
|
|
|
|
setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __cpuinit
|
|
|
|
perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
|
|
|
|
{
|
|
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
|
|
case CPU_STARTING:
|
|
|
|
setup_APIC_ibs(NULL);
|
|
|
|
break;
|
|
|
|
case CPU_DYING:
|
|
|
|
clear_APIC_ibs(NULL);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init int amd_ibs_init(void)
|
|
|
|
{
|
|
|
|
u32 caps;
|
2011-11-08 18:20:44 +00:00
|
|
|
int ret = -EINVAL;
|
2011-09-21 09:30:18 +00:00
|
|
|
|
|
|
|
caps = __get_ibs_caps();
|
|
|
|
if (!caps)
|
|
|
|
return -ENODEV; /* ibs not supported by the cpu */
|
|
|
|
|
2011-11-08 18:20:44 +00:00
|
|
|
/*
|
|
|
|
* Force LVT offset assignment for family 10h: The offsets are
|
|
|
|
* not assigned by the BIOS for this family, so the OS is
|
|
|
|
* responsible for doing it. If the OS assignment fails, fall
|
|
|
|
* back to BIOS settings and try to setup this.
|
|
|
|
*/
|
|
|
|
if (boot_cpu_data.x86 == 0x10)
|
|
|
|
force_ibs_eilvt_setup();
|
|
|
|
|
|
|
|
if (!ibs_eilvt_valid())
|
|
|
|
goto out;
|
2011-09-21 09:30:18 +00:00
|
|
|
|
|
|
|
get_online_cpus();
|
|
|
|
ibs_caps = caps;
|
|
|
|
/* make ibs_caps visible to other cpus: */
|
|
|
|
smp_mb();
|
|
|
|
perf_cpu_notifier(perf_ibs_cpu_notifier);
|
|
|
|
smp_call_function(setup_APIC_ibs, NULL, 1);
|
|
|
|
put_online_cpus();
|
|
|
|
|
2011-11-08 18:20:44 +00:00
|
|
|
ret = perf_event_ibs_init();
|
|
|
|
out:
|
|
|
|
if (ret)
|
|
|
|
pr_err("Failed to setup IBS, %d\n", ret);
|
|
|
|
return ret;
|
2011-09-21 09:30:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Since we need the pci subsystem to init ibs we can't do this earlier: */
|
|
|
|
device_initcall(amd_ibs_init);
|