2009-09-13 14:30:11 +00:00
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/*
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* Driver for the Conexant CX25821 PCIe bridge
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*
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* Copyright (C) 2009 Conexant Systems Inc.
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* Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "cx25821-video.h"
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#include "cx25821-video-upstream.h"
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#include <linux/fs.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/syscalls.h>
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#include <linux/file.h>
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#include <linux/fcntl.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2010-04-06 05:09:00 +00:00
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#include <linux/uaccess.h>
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2009-09-13 14:30:11 +00:00
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MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
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MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
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MODULE_LICENSE("GPL");
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static int _intr_msk =
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FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
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int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
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struct sram_channel *ch,
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unsigned int bpl, u32 risc)
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{
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unsigned int i, lines;
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u32 cdt;
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if (ch->cmds_start == 0) {
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cx_write(ch->ptr1_reg, 0);
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cx_write(ch->ptr2_reg, 0);
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cx_write(ch->cnt2_reg, 0);
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cx_write(ch->cnt1_reg, 0);
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return 0;
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}
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bpl = (bpl + 7) & ~7; /* alignment */
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cdt = ch->cdt;
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lines = ch->fifo_size / bpl;
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2010-04-06 05:09:00 +00:00
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if (lines > 4)
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2009-09-13 14:30:11 +00:00
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lines = 4;
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BUG_ON(lines < 2);
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/* write CDT */
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for (i = 0; i < lines; i++) {
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cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
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cx_write(cdt + 16 * i + 4, 0);
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cx_write(cdt + 16 * i + 8, 0);
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cx_write(cdt + 16 * i + 12, 0);
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}
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/* write CMDS */
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cx_write(ch->cmds_start + 0, risc);
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cx_write(ch->cmds_start + 4, 0);
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cx_write(ch->cmds_start + 8, cdt);
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cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
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cx_write(ch->cmds_start + 16, ch->ctrl_start);
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cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
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for (i = 24; i < 80; i += 4)
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cx_write(ch->cmds_start + i, 0);
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/* fill registers */
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cx_write(ch->ptr1_reg, ch->fifo_start);
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cx_write(ch->ptr2_reg, cdt);
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cx_write(ch->cnt2_reg, (lines * 16) >> 3);
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cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
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return 0;
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}
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static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
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2010-04-06 05:09:00 +00:00
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__le32 *rp, unsigned int offset,
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2009-09-13 14:30:11 +00:00
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unsigned int bpl, u32 sync_line,
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unsigned int lines, int fifo_enable,
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int field_type)
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{
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unsigned int line, i;
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int dist_betwn_starts = bpl * 2;
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*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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if (USE_RISC_NOOP_VIDEO) {
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2010-04-06 05:09:00 +00:00
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for (i = 0; i < NUM_NO_OPS; i++)
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2009-09-13 14:30:11 +00:00
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*(rp++) = cpu_to_le32(RISC_NOOP);
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}
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/* scan lines */
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for (line = 0; line < lines; line++) {
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*(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
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*(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
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*(rp++) = cpu_to_le32(0); /* bits 63-32 */
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if ((lines <= NTSC_FIELD_HEIGHT)
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|| (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
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offset += dist_betwn_starts;
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}
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}
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return rp;
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}
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static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
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dma_addr_t databuf_phys_addr,
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unsigned int offset, u32 sync_line,
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unsigned int bpl, unsigned int lines,
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int fifo_enable, int field_type)
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{
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unsigned int line, i;
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struct sram_channel *sram_ch =
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&dev->sram_channels[dev->_channel_upstream_select];
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int dist_betwn_starts = bpl * 2;
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/* sync instruction */
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2010-04-06 05:09:00 +00:00
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if (sync_line != NO_SYNC_LINE)
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2009-09-13 14:30:11 +00:00
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*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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if (USE_RISC_NOOP_VIDEO) {
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2010-04-06 05:09:00 +00:00
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for (i = 0; i < NUM_NO_OPS; i++)
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2009-09-13 14:30:11 +00:00
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*(rp++) = cpu_to_le32(RISC_NOOP);
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}
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/* scan lines */
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for (line = 0; line < lines; line++) {
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*(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
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*(rp++) = cpu_to_le32(databuf_phys_addr + offset);
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*(rp++) = cpu_to_le32(0); /* bits 63-32 */
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if ((lines <= NTSC_FIELD_HEIGHT)
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2010-04-06 05:09:00 +00:00
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|| (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
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/* to skip the other field line */
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offset += dist_betwn_starts;
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2009-09-13 14:30:11 +00:00
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2010-04-06 05:09:00 +00:00
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/* check if we need to enable the FIFO after the first 4 lines
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* For the upstream video channel, the risc engine will enable
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* the FIFO. */
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2009-09-13 14:30:11 +00:00
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if (fifo_enable && line == 3) {
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*(rp++) = RISC_WRITECR;
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*(rp++) = sram_ch->dma_ctl;
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*(rp++) = FLD_VID_FIFO_EN;
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*(rp++) = 0x00000001;
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}
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}
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return rp;
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}
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int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
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struct pci_dev *pci,
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unsigned int top_offset,
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unsigned int bpl, unsigned int lines)
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{
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__le32 *rp;
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int fifo_enable = 0;
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2010-04-06 05:09:00 +00:00
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/* get line count for single field */
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int singlefield_lines = lines >> 1;
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2009-09-13 14:30:11 +00:00
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int odd_num_lines = singlefield_lines;
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int frame = 0;
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int frame_size = 0;
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int databuf_offset = 0;
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int risc_program_size = 0;
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int risc_flag = RISC_CNT_RESET;
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unsigned int bottom_offset = bpl;
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dma_addr_t risc_phys_jump_addr;
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if (dev->_isNTSC) {
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odd_num_lines = singlefield_lines + 1;
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risc_program_size = FRAME1_VID_PROG_SIZE;
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frame_size =
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(bpl ==
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Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
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FRAME_SIZE_NTSC_Y422;
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} else {
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risc_program_size = PAL_VID_PROG_SIZE;
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frame_size =
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(bpl ==
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Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
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}
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/* Virtual address of Risc buffer program */
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rp = dev->_dma_virt_addr;
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for (frame = 0; frame < NUM_FRAMES; frame++) {
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databuf_offset = frame_size * frame;
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if (UNSET != top_offset) {
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fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
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rp = cx25821_risc_field_upstream(dev, rp,
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dev->
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_data_buf_phys_addr +
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databuf_offset,
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top_offset, 0, bpl,
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odd_num_lines,
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fifo_enable,
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ODD_FIELD);
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}
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fifo_enable = FIFO_DISABLE;
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2010-04-06 05:09:00 +00:00
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/* Even Field */
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2009-09-13 14:30:11 +00:00
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rp = cx25821_risc_field_upstream(dev, rp,
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dev->_data_buf_phys_addr +
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databuf_offset, bottom_offset,
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0x200, bpl, singlefield_lines,
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fifo_enable, EVEN_FIELD);
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if (frame == 0) {
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risc_flag = RISC_CNT_RESET;
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risc_phys_jump_addr =
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dev->_dma_phys_start_addr + risc_program_size;
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} else {
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risc_phys_jump_addr = dev->_dma_phys_start_addr;
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risc_flag = RISC_CNT_INC;
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}
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2010-04-06 05:09:00 +00:00
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/* Loop to 2ndFrameRISC or to Start of Risc
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* program & generate IRQ
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*/
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2009-09-13 14:30:11 +00:00
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*(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
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*(rp++) = cpu_to_le32(risc_phys_jump_addr);
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*(rp++) = cpu_to_le32(0);
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}
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return 0;
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}
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void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
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{
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struct sram_channel *sram_ch =
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&dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I];
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u32 tmp = 0;
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if (!dev->_is_running) {
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printk
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2010-04-06 05:09:00 +00:00
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("cx25821: No video file is currently running so return!\n");
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2009-09-13 14:30:11 +00:00
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return;
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}
|
2010-04-06 05:09:00 +00:00
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/* Disable RISC interrupts */
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2009-09-13 14:30:11 +00:00
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tmp = cx_read(sram_ch->int_msk);
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cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
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|
2010-04-06 05:09:00 +00:00
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/* Turn OFF risc and fifo enable */
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2009-09-13 14:30:11 +00:00
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tmp = cx_read(sram_ch->dma_ctl);
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cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
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2010-04-06 05:09:00 +00:00
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/* Clear data buffer memory */
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2009-09-13 14:30:11 +00:00
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if (dev->_data_buf_virt_addr)
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memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
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dev->_is_running = 0;
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dev->_is_first_frame = 0;
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dev->_frame_count = 0;
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dev->_file_status = END_OF_FILE;
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if (dev->_irq_queues) {
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kfree(dev->_irq_queues);
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dev->_irq_queues = NULL;
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}
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if (dev->_filename != NULL)
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|
|
kfree(dev->_filename);
|
|
|
|
|
|
|
|
tmp = cx_read(VID_CH_MODE_SEL);
|
|
|
|
cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
|
|
|
|
{
|
2010-04-06 05:09:00 +00:00
|
|
|
if (dev->_is_running)
|
2009-09-13 14:30:11 +00:00
|
|
|
cx25821_stop_upstream_video_ch1(dev);
|
|
|
|
|
|
|
|
if (dev->_dma_virt_addr) {
|
|
|
|
pci_free_consistent(dev->pci, dev->_risc_size,
|
|
|
|
dev->_dma_virt_addr, dev->_dma_phys_addr);
|
|
|
|
dev->_dma_virt_addr = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->_data_buf_virt_addr) {
|
|
|
|
pci_free_consistent(dev->pci, dev->_data_buf_size,
|
|
|
|
dev->_data_buf_virt_addr,
|
|
|
|
dev->_data_buf_phys_addr);
|
|
|
|
dev->_data_buf_virt_addr = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
|
|
|
|
{
|
|
|
|
struct file *myfile;
|
|
|
|
int frame_index_temp = dev->_frame_index;
|
|
|
|
int i = 0;
|
|
|
|
int line_size =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
|
|
|
|
int frame_size = 0;
|
|
|
|
int frame_offset = 0;
|
|
|
|
ssize_t vfs_read_retval = 0;
|
|
|
|
char mybuf[line_size];
|
|
|
|
loff_t file_offset;
|
|
|
|
loff_t pos;
|
|
|
|
mm_segment_t old_fs;
|
|
|
|
|
|
|
|
if (dev->_file_status == END_OF_FILE)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (dev->_isNTSC) {
|
|
|
|
frame_size =
|
|
|
|
(line_size ==
|
|
|
|
Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
|
|
|
|
FRAME_SIZE_NTSC_Y422;
|
|
|
|
} else {
|
|
|
|
frame_size =
|
|
|
|
(line_size ==
|
|
|
|
Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
|
|
|
|
}
|
|
|
|
|
|
|
|
frame_offset = (frame_index_temp > 0) ? frame_size : 0;
|
|
|
|
file_offset = dev->_frame_count * frame_size;
|
|
|
|
|
|
|
|
myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
|
|
|
|
|
|
|
|
if (IS_ERR(myfile)) {
|
|
|
|
const int open_errno = -PTR_ERR(myfile);
|
2010-04-06 05:09:00 +00:00
|
|
|
printk("%s(): ERROR opening file(%s) with errno = %d!\n",
|
2009-09-13 14:30:11 +00:00
|
|
|
__func__, dev->_filename, open_errno);
|
|
|
|
return PTR_ERR(myfile);
|
|
|
|
} else {
|
|
|
|
if (!(myfile->f_op)) {
|
|
|
|
printk("%s: File has no file operations registered!",
|
|
|
|
__func__);
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!myfile->f_op->read) {
|
|
|
|
printk("%s: File has no READ operations registered!",
|
|
|
|
__func__);
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
pos = myfile->f_pos;
|
|
|
|
old_fs = get_fs();
|
|
|
|
set_fs(KERNEL_DS);
|
|
|
|
|
|
|
|
for (i = 0; i < dev->_lines_count; i++) {
|
|
|
|
pos = file_offset;
|
|
|
|
|
|
|
|
vfs_read_retval =
|
|
|
|
vfs_read(myfile, mybuf, line_size, &pos);
|
|
|
|
|
|
|
|
if (vfs_read_retval > 0 && vfs_read_retval == line_size
|
|
|
|
&& dev->_data_buf_virt_addr != NULL) {
|
|
|
|
memcpy((void *)(dev->_data_buf_virt_addr +
|
|
|
|
frame_offset / 4), mybuf,
|
|
|
|
vfs_read_retval);
|
|
|
|
}
|
|
|
|
|
|
|
|
file_offset += vfs_read_retval;
|
|
|
|
frame_offset += vfs_read_retval;
|
|
|
|
|
|
|
|
if (vfs_read_retval < line_size) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"Done: exit %s() since no more bytes to read from Video file.\n",
|
|
|
|
__func__);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i > 0)
|
|
|
|
dev->_frame_count++;
|
|
|
|
|
|
|
|
dev->_file_status =
|
|
|
|
(vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
|
|
|
|
|
|
|
|
set_fs(old_fs);
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cx25821_vidups_handler(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct cx25821_dev *dev =
|
|
|
|
container_of(work, struct cx25821_dev, _irq_work_entry);
|
|
|
|
|
|
|
|
if (!dev) {
|
2010-04-06 05:09:00 +00:00
|
|
|
printk("ERROR %s(): since container_of(work_struct) FAILED!\n",
|
2009-09-13 14:30:11 +00:00
|
|
|
__func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
cx25821_get_frame(dev,
|
|
|
|
&dev->sram_channels[dev->_channel_upstream_select]);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
|
|
|
|
{
|
|
|
|
struct file *myfile;
|
|
|
|
int i = 0, j = 0;
|
|
|
|
int line_size =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
|
|
|
|
ssize_t vfs_read_retval = 0;
|
|
|
|
char mybuf[line_size];
|
|
|
|
loff_t pos;
|
|
|
|
loff_t offset = (unsigned long)0;
|
|
|
|
mm_segment_t old_fs;
|
|
|
|
|
|
|
|
myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
|
|
|
|
|
|
|
|
if (IS_ERR(myfile)) {
|
|
|
|
const int open_errno = -PTR_ERR(myfile);
|
2010-04-06 05:09:00 +00:00
|
|
|
printk("%s(): ERROR opening file(%s) with errno = %d!\n",
|
2009-09-13 14:30:11 +00:00
|
|
|
__func__, dev->_filename, open_errno);
|
|
|
|
return PTR_ERR(myfile);
|
|
|
|
} else {
|
|
|
|
if (!(myfile->f_op)) {
|
|
|
|
printk("%s: File has no file operations registered!",
|
|
|
|
__func__);
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!myfile->f_op->read) {
|
|
|
|
printk
|
|
|
|
("%s: File has no READ operations registered! Returning.",
|
|
|
|
__func__);
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
pos = myfile->f_pos;
|
|
|
|
old_fs = get_fs();
|
|
|
|
set_fs(KERNEL_DS);
|
|
|
|
|
|
|
|
for (j = 0; j < NUM_FRAMES; j++) {
|
|
|
|
for (i = 0; i < dev->_lines_count; i++) {
|
|
|
|
pos = offset;
|
|
|
|
|
|
|
|
vfs_read_retval =
|
|
|
|
vfs_read(myfile, mybuf, line_size, &pos);
|
|
|
|
|
|
|
|
if (vfs_read_retval > 0
|
|
|
|
&& vfs_read_retval == line_size
|
|
|
|
&& dev->_data_buf_virt_addr != NULL) {
|
|
|
|
memcpy((void *)(dev->
|
|
|
|
_data_buf_virt_addr +
|
|
|
|
offset / 4), mybuf,
|
|
|
|
vfs_read_retval);
|
|
|
|
}
|
|
|
|
|
|
|
|
offset += vfs_read_retval;
|
|
|
|
|
|
|
|
if (vfs_read_retval < line_size) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"Done: exit %s() since no more bytes to read from Video file.\n",
|
|
|
|
__func__);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i > 0)
|
|
|
|
dev->_frame_count++;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
if (vfs_read_retval < line_size)
|
2009-09-13 14:30:11 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->_file_status =
|
|
|
|
(vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
|
|
|
|
|
|
|
|
set_fs(old_fs);
|
|
|
|
myfile->f_pos = 0;
|
|
|
|
filp_close(myfile, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
|
|
|
|
struct sram_channel *sram_ch, int bpl)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
dma_addr_t data_dma_addr;
|
|
|
|
|
|
|
|
if (dev->_dma_virt_addr != NULL) {
|
|
|
|
pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
|
|
|
|
dev->_dma_virt_addr, dev->_dma_phys_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->_dma_virt_addr =
|
|
|
|
pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
|
|
|
|
&dma_addr);
|
|
|
|
dev->_dma_virt_start_addr = dev->_dma_virt_addr;
|
|
|
|
dev->_dma_phys_start_addr = dma_addr;
|
|
|
|
dev->_dma_phys_addr = dma_addr;
|
|
|
|
dev->_risc_size = dev->upstream_riscbuf_size;
|
|
|
|
|
|
|
|
if (!dev->_dma_virt_addr) {
|
|
|
|
printk
|
|
|
|
("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Clear memory at address */
|
2009-09-13 14:30:11 +00:00
|
|
|
memset(dev->_dma_virt_addr, 0, dev->_risc_size);
|
|
|
|
|
|
|
|
if (dev->_data_buf_virt_addr != NULL) {
|
|
|
|
pci_free_consistent(dev->pci, dev->upstream_databuf_size,
|
|
|
|
dev->_data_buf_virt_addr,
|
|
|
|
dev->_data_buf_phys_addr);
|
|
|
|
}
|
2010-04-06 05:09:00 +00:00
|
|
|
/* For Video Data buffer allocation */
|
2009-09-13 14:30:11 +00:00
|
|
|
dev->_data_buf_virt_addr =
|
|
|
|
pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
|
|
|
|
&data_dma_addr);
|
|
|
|
dev->_data_buf_phys_addr = data_dma_addr;
|
|
|
|
dev->_data_buf_size = dev->upstream_databuf_size;
|
|
|
|
|
|
|
|
if (!dev->_data_buf_virt_addr) {
|
|
|
|
printk
|
|
|
|
("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Clear memory at address */
|
2009-09-13 14:30:11 +00:00
|
|
|
memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
|
|
|
|
|
|
|
|
ret = cx25821_openfile(dev, sram_ch);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Create RISC programs */
|
2009-09-13 14:30:11 +00:00
|
|
|
ret =
|
|
|
|
cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
|
|
|
|
dev->_lines_count);
|
|
|
|
if (ret < 0) {
|
|
|
|
printk(KERN_INFO
|
2010-04-06 05:09:00 +00:00
|
|
|
"cx25821: Failed creating Video Upstream Risc programs!\n");
|
2009-09-13 14:30:11 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
error:
|
2009-09-13 14:30:11 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
|
|
|
|
u32 status)
|
|
|
|
{
|
|
|
|
u32 int_msk_tmp;
|
|
|
|
struct sram_channel *channel = &dev->sram_channels[chan_num];
|
|
|
|
int singlefield_lines = NTSC_FIELD_HEIGHT;
|
|
|
|
int line_size_in_bytes = Y422_LINE_SZ;
|
|
|
|
int odd_risc_prog_size = 0;
|
|
|
|
dma_addr_t risc_phys_jump_addr;
|
|
|
|
__le32 *rp;
|
|
|
|
|
|
|
|
if (status & FLD_VID_SRC_RISC1) {
|
2010-04-06 05:09:00 +00:00
|
|
|
/* We should only process one program per call */
|
2009-09-13 14:30:11 +00:00
|
|
|
u32 prog_cnt = cx_read(channel->gpcnt);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Since we've identified our IRQ, clear our bits from the
|
|
|
|
* interrupt mask and interrupt status registers */
|
2009-09-13 14:30:11 +00:00
|
|
|
int_msk_tmp = cx_read(channel->int_msk);
|
|
|
|
cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
|
|
|
|
cx_write(channel->int_stat, _intr_msk);
|
|
|
|
|
|
|
|
spin_lock(&dev->slock);
|
|
|
|
|
|
|
|
dev->_frame_index = prog_cnt;
|
|
|
|
|
|
|
|
queue_work(dev->_irq_queues, &dev->_irq_work_entry);
|
|
|
|
|
|
|
|
if (dev->_is_first_frame) {
|
|
|
|
dev->_is_first_frame = 0;
|
|
|
|
|
|
|
|
if (dev->_isNTSC) {
|
|
|
|
singlefield_lines += 1;
|
|
|
|
odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
|
|
|
|
} else {
|
|
|
|
singlefield_lines = PAL_FIELD_HEIGHT;
|
|
|
|
odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->_dma_virt_start_addr != NULL) {
|
|
|
|
line_size_in_bytes =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_411) ? Y411_LINE_SZ :
|
|
|
|
Y422_LINE_SZ;
|
|
|
|
risc_phys_jump_addr =
|
|
|
|
dev->_dma_phys_start_addr +
|
|
|
|
odd_risc_prog_size;
|
|
|
|
|
|
|
|
rp = cx25821_update_riscprogram(dev,
|
|
|
|
dev->
|
|
|
|
_dma_virt_start_addr,
|
|
|
|
TOP_OFFSET,
|
|
|
|
line_size_in_bytes,
|
|
|
|
0x0,
|
|
|
|
singlefield_lines,
|
|
|
|
FIFO_DISABLE,
|
|
|
|
ODD_FIELD);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Jump to Even Risc program of 1st Frame */
|
2009-09-13 14:30:11 +00:00
|
|
|
*(rp++) = cpu_to_le32(RISC_JUMP);
|
|
|
|
*(rp++) = cpu_to_le32(risc_phys_jump_addr);
|
|
|
|
*(rp++) = cpu_to_le32(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
} else {
|
|
|
|
if (status & FLD_VID_SRC_UF)
|
|
|
|
printk
|
|
|
|
("%s: Video Received Underflow Error Interrupt!\n",
|
|
|
|
__func__);
|
|
|
|
|
|
|
|
if (status & FLD_VID_SRC_SYNC)
|
|
|
|
printk("%s: Video Received Sync Error Interrupt!\n",
|
|
|
|
__func__);
|
|
|
|
|
|
|
|
if (status & FLD_VID_SRC_OPC_ERR)
|
|
|
|
printk("%s: Video Received OpCode Error Interrupt!\n",
|
|
|
|
__func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->_file_status == END_OF_FILE) {
|
|
|
|
printk("cx25821: EOF Channel 1 Framecount = %d\n",
|
|
|
|
dev->_frame_count);
|
|
|
|
return -1;
|
|
|
|
}
|
2010-04-06 05:09:00 +00:00
|
|
|
/* ElSE, set the interrupt mask register, re-enable irq. */
|
2009-09-13 14:30:11 +00:00
|
|
|
int_msk_tmp = cx_read(channel->int_msk);
|
|
|
|
cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct cx25821_dev *dev = dev_id;
|
|
|
|
u32 msk_stat, vid_status;
|
|
|
|
int handled = 0;
|
|
|
|
int channel_num = 0;
|
|
|
|
struct sram_channel *sram_ch;
|
|
|
|
|
|
|
|
if (!dev)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
|
|
|
|
|
|
|
|
sram_ch = &dev->sram_channels[channel_num];
|
|
|
|
|
|
|
|
msk_stat = cx_read(sram_ch->int_mstat);
|
|
|
|
vid_status = cx_read(sram_ch->int_stat);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Only deal with our interrupt */
|
2009-09-13 14:30:11 +00:00
|
|
|
if (vid_status) {
|
|
|
|
handled =
|
|
|
|
cx25821_video_upstream_irq(dev, channel_num, vid_status);
|
|
|
|
}
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
if (handled < 0)
|
2009-09-13 14:30:11 +00:00
|
|
|
cx25821_stop_upstream_video_ch1(dev);
|
2010-04-06 05:09:00 +00:00
|
|
|
else
|
2009-09-13 14:30:11 +00:00
|
|
|
handled += handled;
|
|
|
|
|
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
|
|
|
|
int pix_format)
|
|
|
|
{
|
|
|
|
int width = WIDTH_D1;
|
|
|
|
int height = dev->_lines_count;
|
|
|
|
int num_lines, odd_num_lines;
|
|
|
|
u32 value;
|
|
|
|
int vip_mode = OUTPUT_FRMT_656;
|
|
|
|
|
|
|
|
value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
|
|
|
|
value &= 0xFFFFFFEF;
|
|
|
|
value |= dev->_isNTSC ? 0 : 0x10;
|
|
|
|
cx_write(ch->vid_fmt_ctl, value);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* set number of active pixels in each line.
|
|
|
|
* Default is 720 pixels in both NTSC and PAL format */
|
2009-09-13 14:30:11 +00:00
|
|
|
cx_write(ch->vid_active_ctl1, width);
|
|
|
|
|
|
|
|
num_lines = (height / 2) & 0x3FF;
|
|
|
|
odd_num_lines = num_lines;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
if (dev->_isNTSC)
|
2009-09-13 14:30:11 +00:00
|
|
|
odd_num_lines += 1;
|
|
|
|
|
|
|
|
value = (num_lines << 16) | odd_num_lines;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* set number of active lines in field 0 (top) and field 1 (bottom) */
|
2009-09-13 14:30:11 +00:00
|
|
|
cx_write(ch->vid_active_ctl2, value);
|
|
|
|
|
|
|
|
cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
|
|
|
|
struct sram_channel *sram_ch)
|
|
|
|
{
|
|
|
|
u32 tmp = 0;
|
|
|
|
int err = 0;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
|
|
|
|
* channel A-C
|
|
|
|
*/
|
2009-09-13 14:30:11 +00:00
|
|
|
tmp = cx_read(VID_CH_MODE_SEL);
|
|
|
|
cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Set the physical start address of the RISC program in the initial
|
|
|
|
* program counter(IPC) member of the cmds.
|
|
|
|
*/
|
2009-09-13 14:30:11 +00:00
|
|
|
cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Risc IPC High 64 bits 63-32 */
|
|
|
|
cx_write(sram_ch->cmds_start + 4, 0);
|
2009-09-13 14:30:11 +00:00
|
|
|
|
|
|
|
/* reset counter */
|
|
|
|
cx_write(sram_ch->gpcnt_ctl, 3);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Clear our bits from the interrupt status register. */
|
2009-09-13 14:30:11 +00:00
|
|
|
cx_write(sram_ch->int_stat, _intr_msk);
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Set the interrupt mask register, enable irq. */
|
2009-09-13 14:30:11 +00:00
|
|
|
cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
|
|
|
|
tmp = cx_read(sram_ch->int_msk);
|
|
|
|
cx_write(sram_ch->int_msk, tmp |= _intr_msk);
|
|
|
|
|
|
|
|
err =
|
|
|
|
request_irq(dev->pci->irq, cx25821_upstream_irq,
|
|
|
|
IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
|
|
|
|
if (err < 0) {
|
|
|
|
printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
|
|
|
|
dev->pci->irq);
|
|
|
|
goto fail_irq;
|
|
|
|
}
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Start the DMA engine */
|
2009-09-13 14:30:11 +00:00
|
|
|
tmp = cx_read(sram_ch->dma_ctl);
|
|
|
|
cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
|
|
|
|
|
|
|
|
dev->_is_running = 1;
|
|
|
|
dev->_is_first_frame = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
fail_irq:
|
2009-09-13 14:30:11 +00:00
|
|
|
cx25821_dev_unregister(dev);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
|
|
|
|
int pixel_format)
|
|
|
|
{
|
|
|
|
struct sram_channel *sram_ch;
|
|
|
|
u32 tmp;
|
|
|
|
int retval = 0;
|
|
|
|
int err = 0;
|
|
|
|
int data_frame_size = 0;
|
|
|
|
int risc_buffer_size = 0;
|
|
|
|
int str_length = 0;
|
|
|
|
|
|
|
|
if (dev->_is_running) {
|
|
|
|
printk("Video Channel is still running so return!\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->_channel_upstream_select = channel_select;
|
|
|
|
sram_ch = &dev->sram_channels[channel_select];
|
|
|
|
|
|
|
|
INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
|
|
|
|
dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
|
|
|
|
|
|
|
|
if (!dev->_irq_queues) {
|
|
|
|
printk
|
|
|
|
("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2010-04-06 05:09:00 +00:00
|
|
|
/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
|
|
|
|
* channel A-C
|
|
|
|
*/
|
2009-09-13 14:30:11 +00:00
|
|
|
tmp = cx_read(VID_CH_MODE_SEL);
|
|
|
|
cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
|
|
|
|
|
|
|
dev->_is_running = 0;
|
|
|
|
dev->_frame_count = 0;
|
|
|
|
dev->_file_status = RESET_STATUS;
|
|
|
|
dev->_lines_count = dev->_isNTSC ? 480 : 576;
|
|
|
|
dev->_pixel_format = pixel_format;
|
|
|
|
dev->_line_size =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
|
|
|
data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
|
|
|
|
risc_buffer_size =
|
|
|
|
dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
|
|
|
|
|
|
|
|
if (dev->input_filename) {
|
|
|
|
str_length = strlen(dev->input_filename);
|
|
|
|
dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!dev->_filename)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
memcpy(dev->_filename, dev->input_filename, str_length + 1);
|
|
|
|
} else {
|
|
|
|
str_length = strlen(dev->_defaultname);
|
|
|
|
dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!dev->_filename)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
memcpy(dev->_filename, dev->_defaultname, str_length + 1);
|
|
|
|
}
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Default if filename is empty string */
|
2009-09-13 14:30:11 +00:00
|
|
|
if (strcmp(dev->input_filename, "") == 0) {
|
|
|
|
if (dev->_isNTSC) {
|
|
|
|
dev->_filename =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_411) ? "/root/vid411.yuv" :
|
|
|
|
"/root/vidtest.yuv";
|
|
|
|
} else {
|
|
|
|
dev->_filename =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_411) ? "/root/pal411.yuv" :
|
|
|
|
"/root/pal422.yuv";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->_is_running = 0;
|
|
|
|
dev->_frame_count = 0;
|
|
|
|
dev->_file_status = RESET_STATUS;
|
|
|
|
dev->_lines_count = dev->_isNTSC ? 480 : 576;
|
|
|
|
dev->_pixel_format = pixel_format;
|
|
|
|
dev->_line_size =
|
|
|
|
(dev->_pixel_format ==
|
|
|
|
PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
|
|
|
|
|
|
|
retval =
|
|
|
|
cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
|
|
|
|
0);
|
|
|
|
|
|
|
|
/* setup fifo + format */
|
|
|
|
cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
|
|
|
|
|
|
|
|
dev->upstream_riscbuf_size = risc_buffer_size * 2;
|
|
|
|
dev->upstream_databuf_size = data_frame_size * 2;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
/* Allocating buffers and prepare RISC program */
|
2009-09-13 14:30:11 +00:00
|
|
|
retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
|
|
|
|
if (retval < 0) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"%s: Failed to set up Video upstream buffers!\n",
|
|
|
|
dev->name);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
cx25821_start_video_dma_upstream(dev, sram_ch);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2010-04-06 05:09:00 +00:00
|
|
|
error:
|
2009-09-13 14:30:11 +00:00
|
|
|
cx25821_dev_unregister(dev);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|