2008-03-03 17:12:55 +00:00
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/*
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* Intel SMP support routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
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* (c) 2002,2003 Andi Kleen, SuSE Labs.
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*
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* i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*/
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2008-03-03 17:12:52 +00:00
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/cache.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <asm/mtrr.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/proto.h>
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#include <mach_ipi.h>
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2008-03-25 16:28:56 +00:00
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#include <mach_apic.h>
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2008-03-03 17:12:55 +00:00
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/*
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* Some notes on x86 processor bugs affecting SMP operation:
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*
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* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
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* The Linux implications for SMP are handled as follows:
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*
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* Pentium III / [Xeon]
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* None of the E1AP-E3AP errata are visible to the user.
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*
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* E1AP. see PII A1AP
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* E2AP. see PII A2AP
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* E3AP. see PII A3AP
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*
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* Pentium II / [Xeon]
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* None of the A1AP-A3AP errata are visible to the user.
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*
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* A1AP. see PPro 1AP
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* A2AP. see PPro 2AP
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* A3AP. see PPro 7AP
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*
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* Pentium Pro
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* None of 1AP-9AP errata are visible to the normal user,
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* except occasional delivery of 'spurious interrupt' as trap #15.
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* This is very rare and a non-problem.
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*
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* 1AP. Linux maps APIC as non-cacheable
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* 2AP. worked around in hardware
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* 3AP. fixed in C0 and above steppings microcode update.
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* Linux does not use excessive STARTUP_IPIs.
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* 4AP. worked around in hardware
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* 5AP. symmetric IO mode (normal Linux operation) not affected.
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* 'noapic' mode has vector 0xf filled out properly.
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* 6AP. 'noapic' mode might be affected - fixed in later steppings
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* 7AP. We do not assume writes to the LVT deassering IRQs
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* 8AP. We do not enable low power mode (deep sleep) during MP bootup
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* 9AP. We do not use mixed mode
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*
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* Pentium
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* There is a marginal case where REP MOVS on 100MHz SMP
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* machines with B stepping processors can fail. XXX should provide
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* an L1cache=Writethrough or L1cache=off option.
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*
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* B stepping CPUs may hang. There are hardware work arounds
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* for this. We warn about it in case your board doesn't have the work
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* arounds. Basically that's so I can tell anyone with a B stepping
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* CPU and SMP problems "tough".
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*
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* Specific items [From Pentium Processor Specification Update]
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*
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* 1AP. Linux doesn't use remote read
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* 2AP. Linux doesn't trust APIC errors
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* 3AP. We work around this
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* 4AP. Linux never generated 3 interrupts of the same priority
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* to cause a lost local interrupt.
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* 5AP. Remote read is never used
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* 6AP. not affected - worked around in hardware
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* 7AP. not affected - worked around in hardware
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* 8AP. worked around in hardware - we get explicit CS errors if not
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* 9AP. only 'noapic' mode affected. Might generate spurious
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* interrupts, we log only the first one and count the
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* rest silently.
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* 10AP. not affected - worked around in hardware
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* 11AP. Linux reads the APIC between writes to avoid this, as per
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* the documentation. Make sure you preserve this as it affects
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* the C stepping chips too.
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* 12AP. not affected - worked around in hardware
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* 13AP. not affected - worked around in hardware
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* 14AP. we always deassert INIT during bootup
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* 15AP. not affected - worked around in hardware
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* 16AP. not affected - worked around in hardware
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* 17AP. not affected - worked around in hardware
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* 18AP. not affected - worked around in hardware
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* 19AP. not affected - worked around in BIOS
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*
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* If this sounds worrying believe me these bugs are either ___RARE___,
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* or are signal timing bugs worked around in hardware and there's
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* about nothing of note with C stepping upwards.
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*/
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2008-03-03 17:12:52 +00:00
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/*
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* this function sends a 'reschedule' IPI to another CPU.
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* it goes straight through and wastes no time serializing
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* anything. Worst case is that we lose a reschedule ...
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*/
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static void native_smp_send_reschedule(int cpu)
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{
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2008-03-10 12:14:03 +00:00
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if (unlikely(cpu_is_offline(cpu))) {
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WARN_ON(1);
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return;
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}
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2008-03-03 17:12:52 +00:00
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send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
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}
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2008-06-26 09:21:54 +00:00
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void native_send_call_func_single_ipi(int cpu)
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2008-03-03 17:12:52 +00:00
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{
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2008-06-26 09:21:54 +00:00
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send_IPI_mask(cpumask_of_cpu(cpu), CALL_FUNCTION_SINGLE_VECTOR);
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2008-03-03 17:12:52 +00:00
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}
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2008-06-26 09:21:54 +00:00
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void native_send_call_func_ipi(cpumask_t mask)
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2008-03-03 17:12:52 +00:00
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{
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cpumask_t allbutself;
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allbutself = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutself);
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x86: fix app crashes after SMP resume
After resume on a 2cpu laptop, kernel builds collapse with a sed hang,
sh or make segfault (often on 20295564), real-time signal to cc1 etc.
Several hurdles to jump, but a manually-assisted bisect led to -rc1's
d2bcbad5f3ad38a1c09861bca7e252dde7bb8259 x86: do not zap_low_mappings
in __smp_prepare_cpus. Though the low mappings were removed at bootup,
they were left behind (with Global flags helping to keep them in TLB)
after resume or cpu online, causing the crashes seen.
Reinstate zap_low_mappings (with local __flush_tlb_all) for each cpu_up
on x86_32. This used to be serialized by smp_commenced_mask: that's now
gone, but a low_mappings flag will do. No need for native_smp_cpus_done
to repeat the zap: let mem_init zap BSP's low mappings just like on UP.
(In passing, fix error code from native_cpu_up: do_boot_cpu returns a
variety of diagnostic values, Dprintk what it says but convert to -EIO.
And save_pg_dir separately before zap_low_mappings: doesn't matter now,
but zapping twice in succession wiped out resume's swsusp_pg_dir.)
That worked well on the duo and one quad, but wouldn't boot 3rd or 4th
cpu on P4 Xeon, oopsing just after unlock_ipi_call_lock. The TLB flush
IPI now being sent reveals a long-standing bug: the booting cpu has its
APIC readied in smp_callin at the top of start_secondary, but isn't put
into the cpu_online_map until just before that unlock_ipi_call_lock.
So native_smp_call_function_mask to online cpus would send_IPI_allbutself,
including the cpu just coming up, though it has been excluded from the
count to wait for: by the time it handles the IPI, the call data on
native_smp_call_function_mask's stack may well have been overwritten.
So fall back to send_IPI_mask while cpu_online_map does not match
cpu_callout_map: perhaps there's a better APICological fix to be
made at the start_secondary end, but I wouldn't know that.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-13 13:26:57 +00:00
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if (cpus_equal(mask, allbutself) &&
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cpus_equal(cpu_online_map, cpu_callout_map))
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2008-03-03 17:12:52 +00:00
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send_IPI_allbutself(CALL_FUNCTION_VECTOR);
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else
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send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
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}
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static void stop_this_cpu(void *dummy)
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{
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local_irq_disable();
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/*
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* Remove this CPU:
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*/
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cpu_clear(smp_processor_id(), cpu_online_map);
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disable_local_APIC();
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if (hlt_works(smp_processor_id()))
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for (;;) halt();
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for (;;);
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}
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/*
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* this function calls the 'stop' function on all other CPUs in the system.
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*/
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static void native_smp_send_stop(void)
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{
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unsigned long flags;
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if (reboot_force)
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return;
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2008-06-06 09:18:06 +00:00
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smp_call_function(stop_this_cpu, NULL, 0);
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2008-03-03 17:12:52 +00:00
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local_irq_save(flags);
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disable_local_APIC();
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local_irq_restore(flags);
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}
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/*
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* Reschedule call back. Nothing to do,
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* all the work is done automatically when
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* we return from the interrupt.
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*/
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void smp_reschedule_interrupt(struct pt_regs *regs)
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{
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ack_APIC_irq();
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#ifdef CONFIG_X86_32
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__get_cpu_var(irq_stat).irq_resched_count++;
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#else
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add_pda(irq_resched_count, 1);
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#endif
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}
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void smp_call_function_interrupt(struct pt_regs *regs)
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{
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ack_APIC_irq();
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irq_enter();
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2008-06-26 09:21:54 +00:00
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generic_smp_call_function_interrupt();
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2008-03-03 17:12:52 +00:00
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#ifdef CONFIG_X86_32
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__get_cpu_var(irq_stat).irq_call_count++;
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#else
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add_pda(irq_call_count, 1);
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#endif
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irq_exit();
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2008-06-26 09:21:54 +00:00
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}
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2008-03-03 17:12:52 +00:00
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2008-06-26 09:21:54 +00:00
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void smp_call_function_single_interrupt(void)
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{
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ack_APIC_irq();
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irq_enter();
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generic_smp_call_function_single_interrupt();
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#ifdef CONFIG_X86_32
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__get_cpu_var(irq_stat).irq_call_count++;
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#else
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add_pda(irq_call_count, 1);
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#endif
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irq_exit();
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2008-03-03 17:12:52 +00:00
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}
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struct smp_ops smp_ops = {
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.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
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.smp_prepare_cpus = native_smp_prepare_cpus,
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.cpu_up = native_cpu_up,
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.smp_cpus_done = native_smp_cpus_done,
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.smp_send_stop = native_smp_send_stop,
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.smp_send_reschedule = native_smp_send_reschedule,
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2008-06-26 09:21:54 +00:00
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.send_call_func_ipi = native_send_call_func_ipi,
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.send_call_func_single_ipi = native_send_call_func_single_ipi,
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2008-03-03 17:12:52 +00:00
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};
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EXPORT_SYMBOL_GPL(smp_ops);
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