blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
/*
|
2007-07-24 07:23:20 +00:00
|
|
|
* File: include/asm-blackfin/mach-bf537/anomaly.h
|
|
|
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
*
|
2008-05-31 07:47:17 +00:00
|
|
|
* Copyright (C) 2004-2008 Analog Devices Inc.
|
2007-07-24 07:23:20 +00:00
|
|
|
* Licensed under the GPL-2 or later.
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
/* This file shoule be up to date with:
|
2008-04-24 19:28:10 +00:00
|
|
|
* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef _MACH_ANOMALY_H_
|
|
|
|
#define _MACH_ANOMALY_H_
|
|
|
|
|
|
|
|
/* We do not support 0.1 silicon - sorry */
|
2007-07-25 03:19:14 +00:00
|
|
|
#if __SILICON_REVISION__ < 2
|
2007-12-24 12:05:09 +00:00
|
|
|
# error will not work on BF537 silicon version 0.0 or 0.1
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
#endif
|
|
|
|
|
2007-07-25 03:19:14 +00:00
|
|
|
#if defined(__ADSPBF534__)
|
|
|
|
# define ANOMALY_BF534 1
|
|
|
|
#else
|
|
|
|
# define ANOMALY_BF534 0
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
#endif
|
2007-07-25 03:19:14 +00:00
|
|
|
#if defined(__ADSPBF536__)
|
|
|
|
# define ANOMALY_BF536 1
|
|
|
|
#else
|
|
|
|
# define ANOMALY_BF536 0
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
#endif
|
2007-07-25 03:19:14 +00:00
|
|
|
#if defined(__ADSPBF537__)
|
|
|
|
# define ANOMALY_BF537 1
|
|
|
|
#else
|
|
|
|
# define ANOMALY_BF537 0
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
#endif
|
|
|
|
|
2007-07-25 03:19:14 +00:00
|
|
|
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
|
|
|
#define ANOMALY_05000074 (1)
|
|
|
|
/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
|
|
|
|
#define ANOMALY_05000119 (1)
|
|
|
|
/* Rx.H cannot be used to access 16-bit System MMR registers */
|
|
|
|
#define ANOMALY_05000122 (1)
|
|
|
|
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
|
|
|
|
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
|
2007-12-24 12:05:09 +00:00
|
|
|
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
|
|
|
|
#define ANOMALY_05000167 (1)
|
2007-07-25 03:19:14 +00:00
|
|
|
/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
|
|
|
|
#define ANOMALY_05000180 (1)
|
|
|
|
/* Instruction Cache Is Not Functional */
|
|
|
|
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
|
|
|
|
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
|
|
|
|
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Spurious Hardware Error from an access in the shadow of a conditional branch */
|
|
|
|
#define ANOMALY_05000245 (1)
|
|
|
|
/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
|
|
|
|
#define ANOMALY_05000247 (1)
|
|
|
|
/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
|
|
|
|
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
|
|
|
|
/* EMAC Tx DMA error after an early frame abort */
|
|
|
|
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Maximum external clock speed for Timers */
|
|
|
|
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
|
|
|
|
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
|
|
|
|
/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
|
|
|
|
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
|
|
|
|
/* EMAC MDIO input latched on wrong MDC edge */
|
|
|
|
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
|
|
|
|
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
|
|
|
|
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
|
|
|
|
/* ICPLB_STATUS MMR register may be corrupted */
|
|
|
|
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
|
|
|
|
/* DCPLB_FAULT_ADDR MMR register may be corrupted */
|
|
|
|
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Stores to data cache may be lost */
|
|
|
|
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
|
|
|
|
/* Hardware loop corrupted when taking an ICPLB exception */
|
|
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#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
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/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
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#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
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/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
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#define ANOMALY_05000265 (1)
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/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
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#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
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/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
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/* Certain data cache write through modes fail for VDDint <=0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM memory may be lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
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/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
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/* Disabling Peripherals with DMA running may cause DMA system instability */
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#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
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/* SPI Master boot mode does not work well with Atmel Data flash devices */
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#define ANOMALY_05000280 (1)
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/* False Hardware Error Exception when ISR context is not restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
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/* Memory DMA corruption with 32-bit data and traffic control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
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/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
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/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
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#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
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/* SPORTs may receive bad data if FIFOs fill up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
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/* Memory to memory DMA source/destination descriptors must be in same memory space */
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#define ANOMALY_05000301 (1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
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/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
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#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
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/* False hardware errors caused by fetches at the boundary of reserved memory */
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#define ANOMALY_05000310 (1)
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/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
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#define ANOMALY_05000312 (1)
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/* PPI is level sensitive on first transfer */
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#define ANOMALY_05000313 (1)
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/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
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/* EMAC RMII mode: collisions occur in Full Duplex mode */
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#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
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/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
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#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
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/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
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#define ANOMALY_05000322 (1)
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2007-12-24 12:05:09 +00:00
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
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2008-05-31 07:47:17 +00:00
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/* New Feature: UART Remains Enabled after UART Boot */
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#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
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2008-04-24 19:28:10 +00:00
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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2007-12-24 12:05:09 +00:00
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000359 (1)
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2008-04-24 19:28:10 +00:00
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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2008-05-31 07:47:17 +00:00
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#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
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2008-04-24 19:28:10 +00:00
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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2008-10-28 08:22:41 +00:00
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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2008-04-24 19:28:10 +00:00
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2007-07-25 03:19:14 +00:00
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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2007-10-10 15:55:26 +00:00
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#define ANOMALY_05000158 (0)
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2007-07-25 03:19:14 +00:00
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000198 (0)
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2007-08-05 08:53:10 +00:00
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#define ANOMALY_05000230 (0)
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2007-07-25 03:19:14 +00:00
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000311 (0)
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2007-10-10 08:58:49 +00:00
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#define ANOMALY_05000323 (0)
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2008-10-10 13:07:55 +00:00
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#define ANOMALY_05000353 (1)
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2008-04-24 19:28:10 +00:00
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#define ANOMALY_05000363 (0)
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2008-10-10 13:07:55 +00:00
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#define ANOMALY_05000386 (1)
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2007-07-25 03:19:14 +00:00
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#endif
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