2008-08-21 21:04:55 +00:00
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/*
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* Copyright <EFBFBD> 1997-2007 Alacritech, Inc. All rights reserved
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*
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* $Id: sxghif.h,v 1.5 2008/07/24 19:18:22 chris Exp $
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*
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* sxghif.h:
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*
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* This file contains structures and definitions for the
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* Alacritech Sahara host interface
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*/
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/*******************************************************************************
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* UCODE Registers
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*******************************************************************************/
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typedef struct _SXG_UCODE_REGS {
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// Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
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u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
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u32 RsvdReg1; // Code = 1 - TOE -NA
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u32 RsvdReg2; // Code = 2 - TOE -NA
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u32 RsvdReg3; // Code = 3 - TOE -NA
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u32 RsvdReg4; // Code = 4 - TOE -NA
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u32 RsvdReg5; // Code = 5 - TOE -NA
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u32 CardUp; // Code = 6 - Microcode initialized when 1
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u32 RsvdReg7; // Code = 7 - TOE -NA
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u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0
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// This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
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u32 Isp; // Code = 0 (extended), ExCode = 1
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u32 PadEx1[15]; // Codes 1-15 not used with extended codes
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// ExCode 2 = Interrupt Status Register
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u32 Isr; // Code = 0 (extended), ExCode = 2
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u32 PadEx2[15];
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// ExCode 3 = Event base register. Location of event rings
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u32 EventBase; // Code = 0 (extended), ExCode = 3
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u32 PadEx3[15];
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// ExCode 4 = Event ring size
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u32 EventSize; // Code = 0 (extended), ExCode = 4
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u32 PadEx4[15];
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// ExCode 5 = TCB Buffers base address
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u32 TcbBase; // Code = 0 (extended), ExCode = 5
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u32 PadEx5[15];
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// ExCode 6 = TCB Composite Buffers base address
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u32 TcbCompBase; // Code = 0 (extended), ExCode = 6
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u32 PadEx6[15];
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// ExCode 7 = Transmit ring base address
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u32 XmtBase; // Code = 0 (extended), ExCode = 7
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u32 PadEx7[15];
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// ExCode 8 = Transmit ring size
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u32 XmtSize; // Code = 0 (extended), ExCode = 8
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u32 PadEx8[15];
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// ExCode 9 = Receive ring base address
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u32 RcvBase; // Code = 0 (extended), ExCode = 9
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u32 PadEx9[15];
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// ExCode 10 = Receive ring size
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u32 RcvSize; // Code = 0 (extended), ExCode = 10
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u32 PadEx10[15];
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// ExCode 11 = Read EEPROM Config
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u32 Config; // Code = 0 (extended), ExCode = 11
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u32 PadEx11[15];
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// ExCode 12 = Multicast bits 31:0
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u32 McastLow; // Code = 0 (extended), ExCode = 12
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u32 PadEx12[15];
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// ExCode 13 = Multicast bits 63:32
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u32 McastHigh; // Code = 0 (extended), ExCode = 13
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u32 PadEx13[15];
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// ExCode 14 = Ping
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u32 Ping; // Code = 0 (extended), ExCode = 14
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u32 PadEx14[15];
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// ExCode 15 = Link MTU
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u32 LinkMtu; // Code = 0 (extended), ExCode = 15
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u32 PadEx15[15];
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// ExCode 16 = Download synchronization
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u32 LoadSync; // Code = 0 (extended), ExCode = 16
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u32 PadEx16[15];
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// ExCode 17 = Upper DRAM address bits on 32-bit systems
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u32 Upper; // Code = 0 (extended), ExCode = 17
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u32 PadEx17[15];
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// ExCode 18 = Slowpath Send Index Address
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u32 SPSendIndex; // Code = 0 (extended), ExCode = 18
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u32 PadEx18[15];
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u32 RsvdXF; // Code = 0 (extended), ExCode = 19
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u32 PadEx19[15];
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// ExCode 20 = Aggregation
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u32 Aggregation; // Code = 0 (extended), ExCode = 20
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u32 PadEx20[15];
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// ExCode 21 = Receive MDL push timer
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u32 PushTicks; // Code = 0 (extended), ExCode = 21
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u32 PadEx21[15];
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// ExCode 22 = TOE NA
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u32 AckFrequency; // Code = 0 (extended), ExCode = 22
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u32 PadEx22[15];
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// ExCode 23 = TOE NA
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u32 RsvdReg23;
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u32 PadEx23[15];
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// ExCode 24 = TOE NA
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u32 RsvdReg24;
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u32 PadEx24[15];
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// ExCode 25 = TOE NA
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u32 RsvdReg25; // Code = 0 (extended), ExCode = 25
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u32 PadEx25[15];
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// ExCode 26 = Receive checksum requirements
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u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26
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u32 PadEx26[15];
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// ExCode 27 = RSS Requirements
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u32 Rss; // Code = 0 (extended), ExCode = 27
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u32 PadEx27[15];
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// ExCode 28 = RSS Table
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u32 RssTable; // Code = 0 (extended), ExCode = 28
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u32 PadEx28[15];
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// ExCode 29 = Event ring release entries
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u32 EventRelease; // Code = 0 (extended), ExCode = 29
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u32 PadEx29[15];
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// ExCode 30 = Number of receive bufferlist commands on ring 0
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u32 RcvCmd; // Code = 0 (extended), ExCode = 30
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u32 PadEx30[15];
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// ExCode 31 = slowpath transmit command - Data[31:0] = 1
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u32 XmtCmd; // Code = 0 (extended), ExCode = 31
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u32 PadEx31[15];
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// ExCode 32 = Dump command
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u32 DumpCmd; // Code = 0 (extended), ExCode = 32
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u32 PadEx32[15];
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// ExCode 33 = Debug command
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u32 DebugCmd; // Code = 0 (extended), ExCode = 33
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u32 PadEx33[15];
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// There are 128 possible extended commands - each of account for 16
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// words (including the non-relevent base command codes 1-15).
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// Pad for the remainder of these here to bring us to the next CPU
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// base. As extended codes are added, reduce the first array value in
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// the following field
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u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
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} SXG_UCODE_REGS, *PSXG_UCODE_REGS;
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// Interrupt control register (0) values
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#define SXG_ICR_DISABLE 0x00000000
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#define SXG_ICR_ENABLE 0x00000001
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#define SXG_ICR_MASK 0x00000002
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#define SXG_ICR_MSGID_MASK 0xFFFF0000
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#define SXG_ICR_MSGID_SHIFT 16
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#define SXG_ICR(_MessageId, _Data) \
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((((_MessageId) << SXG_ICR_MSGID_SHIFT) & \
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SXG_ICR_MSGID_MASK) | (_Data))
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// The Microcode supports up to 16 RSS queues
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#define SXG_MAX_RSS 16
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#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max
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#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6
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#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4
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#define SXG_RSS_LEGACY 0x00000004 // Line-base interrupts
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#define SXG_RSS_TABLE_SIZE 0x0000FF00 // Table size mask
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#define SXG_RSS_TABLE_SHIFT 8
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#define SXG_RSS_BASE_CPU 0x00FF0000 // Base CPU (not used)
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#define SXG_RSS_BASE_SHIFT 16
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#define SXG_RCV_IP_CSUM_ENABLED 0x00000001 // ExCode 26 (ReceiveChecksum)
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#define SXG_RCV_TCP_CSUM_ENABLED 0x00000002 // ExCode 26 (ReceiveChecksum)
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#define SXG_XMT_CPUID_SHIFT 16
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#if VPCI
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#define SXG_CHECK_FOR_HANG_TIME 3000
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#else
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#define SXG_CHECK_FOR_HANG_TIME 5
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#endif
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/*
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* TCB registers - This is really the same register memory area as UCODE_REGS
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* above, but defined differently. Bits 17:06 of the address define the TCB,
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* which means each TCB area occupies 0x40 (64) bytes, or 16 u32S. What really
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* is happening is that these registers occupy the "PadEx[15]" areas in the
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* SXG_UCODE_REGS definition above
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*/
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typedef struct _SXG_TCB_REGS {
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u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
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u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
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u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
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u32 Rsvd1; /* Code = 3 - TOE NA */
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u32 Rsvd2; /* Code = 4 - TOE NA */
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u32 Rsvd3; /* Code = 5 - TOE NA */
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u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */
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u32 Rsvd4; /* Code = 7 - TOE NA */
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u32 Rsvd5; /* Code = 8 - TOE NA */
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u32 Pad[7]; /* Codes 8-15 - Not used. */
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} SXG_TCB_REGS, *PSXG_TCB_REGS;
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/***************************************************************************
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* ISR Format
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* 31 0
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* _______________________________________
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* | | | | | | | | |
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* |____|____|____|____|____|____|____|____|
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* ^^^^ ^^^^ ^^^^ ^^^^ \ /
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* ERR --|||| |||| |||| |||| -----------------
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* EVENT ---||| |||| |||| |||| |
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* ----|| |||| |||| |||| |-- Crash Address
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* UPC -----| |||| |||| ||||
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* LEVENT -------|||| |||| ||||
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* PDQF --------||| |||| ||||
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* RMISS ---------|| |||| ||||
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* BREAK ----------| |||| ||||
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* HBEATOK ------------|||| ||||
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* NOHBEAT -------------||| ||||
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* ERFULL --------------|| ||||
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* XDROP ---------------| ||||
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* -----------------||||
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* -----------------||||--\
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* ||---|-CpuId of crash
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* |----/
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***************************************************************************/
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#define SXG_ISR_ERR 0x80000000 // Error
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#define SXG_ISR_EVENT 0x40000000 // Event ring event
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#define SXG_ISR_NONE1 0x20000000 // Not used
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#define SXG_ISR_UPC 0x10000000 // Dump/debug command complete
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#define SXG_ISR_LINK 0x08000000 // Link event
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#define SXG_ISR_PDQF 0x04000000 // Processed data queue full
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#define SXG_ISR_RMISS 0x02000000 // Drop - no host buf
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#define SXG_ISR_BREAK 0x01000000 // Breakpoint hit
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#define SXG_ISR_PING 0x00800000 // Heartbeat response
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#define SXG_ISR_DEAD 0x00400000 // Card crash
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#define SXG_ISR_ERFULL 0x00200000 // Event ring full
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#define SXG_ISR_XDROP 0x00100000 // XMT Drop - no DRAM bufs or XMT err
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#define SXG_ISR_SPSEND 0x00080000 // Slow send complete
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#define SXG_ISR_CPU 0x00070000 // Dead CPU mask
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#define SXG_ISR_CPU_SHIFT 16 // Dead CPU shift
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#define SXG_ISR_CRASH 0x0000FFFF // Crash address mask
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/***************************************************************************
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*
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* Event Ring entry
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*
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***************************************************************************/
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/*
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* 31 15 0
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* .___________________.___________________.
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* |<------------ Pad 0 ------------>|
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* |_________|_________|_________|_________|0 0x00
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* |<------------ Pad 1 ------------>|
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* |_________|_________|_________|_________|4 0x04
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* |<------------ Pad 2 ------------>|
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* |_________|_________|_________|_________|8 0x08
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* |<----------- Event Word 0 ------------>|
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* |_________|_________|_________|_________|12 0x0c
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* |<----------- Event Word 1 ------------>|
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* |_________|_________|_________|_________|16 0x10
|
|
|
|
|
* |<------------- Toeplitz ------------>|
|
|
|
|
|
* |_________|_________|_________|_________|20 0x14
|
|
|
|
|
* |<----- Length ---->|<------ TCB Id --->|
|
|
|
|
|
* |_________|_________|_________|_________|24 0x18
|
|
|
|
|
* |<----- Status ---->|Evnt Code|Flsh Code|
|
|
|
|
|
* |_________|_________|_________|_________|28 0x1c
|
|
|
|
|
* ^ ^^^^ ^^^^
|
|
|
|
|
* |- VALID |||| ||||- RBUFC
|
|
|
|
|
* |||| |||-- SLOWR
|
|
|
|
|
* |||| ||--- UNUSED
|
|
|
|
|
* |||| |---- FASTC
|
|
|
|
|
* ||||------ FASTR
|
|
|
|
|
* |||-------
|
|
|
|
|
* ||--------
|
|
|
|
|
* |---------
|
|
|
|
|
*
|
|
|
|
|
* Slowpath status:
|
|
|
|
|
* _______________________________________
|
|
|
|
|
* |<----- Status ---->|Evnt Code|Flsh Code|
|
|
|
|
|
* |_________|Cmd Index|_________|_________|28 0x1c
|
|
|
|
|
* ^^^ ^^^^
|
|
|
|
|
* ||| ||||- ISTCPIP6
|
|
|
|
|
* ||| |||-- IPONLY
|
|
|
|
|
* ||| ||--- RCVERR
|
|
|
|
|
* ||| |---- IPCBAD
|
|
|
|
|
* |||------ TCPCBAD
|
|
|
|
|
* ||------- ISTCPIP
|
|
|
|
|
* |-------- SCERR
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
#pragma pack(push, 1)
|
|
|
|
|
typedef struct _SXG_EVENT {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
u32 Pad[1]; // not used
|
|
|
|
|
u32 SndUna; // SndUna value
|
|
|
|
|
u32 Resid; // receive MDL resid
|
2008-08-21 21:04:55 +00:00
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
void *HostHandle; // Receive host handle
|
|
|
|
|
u32 Rsvd1; // TOE NA
|
2008-08-21 21:04:55 +00:00
|
|
|
|
struct {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
u32 NotUsed;
|
|
|
|
|
u32 Rsvd2; // TOE NA
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} Flush;
|
|
|
|
|
};
|
2008-10-14 22:00:15 +00:00
|
|
|
|
u32 Toeplitz; // RSS Toeplitz hash
|
2008-08-21 21:04:55 +00:00
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort Rsvd3; // TOE NA
|
|
|
|
|
ushort HdrOffset; // Slowpath
|
2008-08-21 21:04:55 +00:00
|
|
|
|
};
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort Length; //
|
|
|
|
|
unsigned char Rsvd4; // TOE NA
|
|
|
|
|
unsigned char Code; // Event code
|
|
|
|
|
unsigned char CommandIndex; // New ring index
|
|
|
|
|
unsigned char Status; // Event status
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_EVENT, *PSXG_EVENT;
|
|
|
|
|
#pragma pack(pop)
|
|
|
|
|
|
|
|
|
|
// Event code definitions
|
|
|
|
|
#define EVENT_CODE_BUFFERS 0x01 // Receive buffer list command (ring 0)
|
|
|
|
|
#define EVENT_CODE_SLOWRCV 0x02 // Slowpath receive
|
|
|
|
|
#define EVENT_CODE_UNUSED 0x04 // Was slowpath commands complete
|
|
|
|
|
|
|
|
|
|
// Status values
|
|
|
|
|
#define EVENT_STATUS_VALID 0x80 // Entry valid
|
|
|
|
|
|
|
|
|
|
// Slowpath status
|
|
|
|
|
#define EVENT_STATUS_ERROR 0x40 // Completed with error. Index in next byte
|
|
|
|
|
#define EVENT_STATUS_TCPIP4 0x20 // TCPIPv4 frame
|
|
|
|
|
#define EVENT_STATUS_TCPBAD 0x10 // Bad TCP checksum
|
|
|
|
|
#define EVENT_STATUS_IPBAD 0x08 // Bad IP checksum
|
|
|
|
|
#define EVENT_STATUS_RCVERR 0x04 // Slowpath receive error
|
|
|
|
|
#define EVENT_STATUS_IPONLY 0x02 // IP frame
|
|
|
|
|
#define EVENT_STATUS_TCPIP6 0x01 // TCPIPv6 frame
|
|
|
|
|
#define EVENT_STATUS_TCPIP 0x21 // Combination of v4 and v6
|
|
|
|
|
|
|
|
|
|
// Event ring
|
|
|
|
|
// Size must be power of 2, between 128 and 16k
|
|
|
|
|
#define EVENT_RING_SIZE 4096 // ??
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
|
|
|
|
|
#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
|
|
typedef struct _SXG_EVENT_RING {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_EVENT Ring[EVENT_RING_SIZE];
|
|
|
|
|
} SXG_EVENT_RING, *PSXG_EVENT_RING;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
*
|
|
|
|
|
* TCB Buffers
|
|
|
|
|
*
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
// Maximum number of TCBS supported by hardware/microcode
|
|
|
|
|
#define SXG_MAX_TCB 4096
|
|
|
|
|
// Minimum TCBs before we fail initialization
|
|
|
|
|
#define SXG_MIN_TCB 512
|
|
|
|
|
// TCB Hash
|
|
|
|
|
// The bucket is determined by bits 11:4 of the toeplitz if we support 4k
|
|
|
|
|
// offloaded connections, 10:4 if we support 2k and so on.
|
|
|
|
|
#define SXG_TCB_BUCKET_SHIFT 4
|
|
|
|
|
#define SXG_TCB_PER_BUCKET 16
|
|
|
|
|
#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID
|
|
|
|
|
#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
|
|
#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct
|
|
|
|
|
|
|
|
|
|
#define SXG_TCB_RCVQ_SIZE 736
|
|
|
|
|
|
|
|
|
|
#define SXG_TCB_COMPOSITE_BUFFER_SIZE 1024
|
|
|
|
|
|
|
|
|
|
#define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
|
|
|
|
|
(((_TcpObject)->VlanId) ? \
|
|
|
|
|
((_IPv6) ? /* Vlan frame header = yes */ \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp : \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp) : \
|
|
|
|
|
((_IPv6) ? /* Vlan frame header = No */ \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
|
|
|
|
|
|
|
|
|
|
#define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
|
|
|
|
|
(_TcpObject)->VlanId ? \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip : \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
|
|
|
|
|
|
|
|
|
|
#define SXG_LOCATE_IP6_FRAME_HDR(_TcpObject) \
|
|
|
|
|
(_TcpObject)->VlanId ? \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
|
|
|
|
|
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
|
|
|
|
|
|
|
|
|
|
#if DBG
|
|
|
|
|
// Horrible kludge to distinguish dumb-nic, slowpath, and
|
|
|
|
|
// fastpath traffic. Decrement the HopLimit by one
|
|
|
|
|
// for slowpath, two for fastpath. This assumes the limit is measurably
|
|
|
|
|
// greater than two, which I think is reasonable.
|
|
|
|
|
// Obviously this is DBG only. Maybe remove later, or #if 0 so we
|
|
|
|
|
// can set it when needed
|
|
|
|
|
#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
|
|
|
|
|
PIPV6_HDR _Ip6FrameHdr; \
|
|
|
|
|
if((_TcpObject)->IPv6) { \
|
|
|
|
|
_Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
|
|
|
|
|
if(_FastPath) { \
|
|
|
|
|
_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 2; \
|
|
|
|
|
} else { \
|
|
|
|
|
_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 1; \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
// Do nothing with free build
|
|
|
|
|
#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
* Receive and transmit rings
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
#define SXG_MAX_RING_SIZE 256
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define SXG_XMT_RING_SIZE 128 // Start with 128
|
|
|
|
|
#define SXG_RCV_RING_SIZE 128 // Start with 128
|
2008-08-21 21:04:55 +00:00
|
|
|
|
#define SXG_MAX_ENTRIES 4096
|
|
|
|
|
|
|
|
|
|
// Structure and macros to manage a ring
|
|
|
|
|
typedef struct _SXG_RING_INFO {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
|
|
|
|
|
unsigned char Tail; // Where we pull off completed entries
|
|
|
|
|
ushort Size; // Ring size - Must be multiple of 2
|
|
|
|
|
void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RING_INFO, *PSXG_RING_INFO;
|
|
|
|
|
|
|
|
|
|
#define SXG_INITIALIZE_RING(_ring, _size) { \
|
|
|
|
|
(_ring).Head = 0; \
|
|
|
|
|
(_ring).Tail = 0; \
|
|
|
|
|
(_ring).Size = (_size); \
|
|
|
|
|
}
|
|
|
|
|
#define SXG_ADVANCE_INDEX(_index, _size) ((_index) = ((_index) + 1) & ((_size) - 1))
|
|
|
|
|
#define SXG_PREVIOUS_INDEX(_index, _size) (((_index) - 1) &((_size) - 1))
|
|
|
|
|
#define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
|
|
|
|
|
#define SXG_RING_FULL(_ring) ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
|
|
|
|
|
#define SXG_RING_ADVANCE_HEAD(_ring) SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
|
|
|
|
|
#define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
|
|
|
|
|
SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
|
|
|
|
|
#define SXG_RING_ADVANCE_TAIL(_ring) { \
|
|
|
|
|
ASSERT((_ring)->Tail != (_ring)->Head); \
|
|
|
|
|
SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size)); \
|
|
|
|
|
}
|
|
|
|
|
// Set cmd to the next available ring entry, set the shadow context
|
|
|
|
|
// entry and advance the ring.
|
|
|
|
|
// The appropriate lock must be held when calling this macro
|
|
|
|
|
#define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) { \
|
|
|
|
|
if(SXG_RING_FULL(_ringinfo)) { \
|
|
|
|
|
(_cmd) = NULL; \
|
|
|
|
|
} else { \
|
|
|
|
|
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head]; \
|
|
|
|
|
(_ringinfo)->Context[(_ringinfo)->Head] = (void *)(_context);\
|
|
|
|
|
SXG_RING_ADVANCE_HEAD(_ringinfo); \
|
|
|
|
|
} \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Abort the previously allocated command by retreating the head.
|
|
|
|
|
// NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
|
|
|
|
|
// and SXG_ABORT_CMD calls.
|
|
|
|
|
#define SXG_ABORT_CMD(_ringinfo) { \
|
|
|
|
|
ASSERT(!(SXG_RING_EMPTY(_ringinfo))); \
|
|
|
|
|
SXG_RING_RETREAT_HEAD(_ringinfo); \
|
|
|
|
|
(_ringinfo)->Context[(_ringinfo)->Head] = NULL; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// For the given ring, return a pointer to the tail cmd and context,
|
|
|
|
|
// clear the context and advance the tail
|
|
|
|
|
#define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) { \
|
|
|
|
|
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail]; \
|
|
|
|
|
(_context) = (_ringinfo)->Context[(_ringinfo)->Tail]; \
|
|
|
|
|
(_ringinfo)->Context[(_ringinfo)->Tail] = NULL; \
|
|
|
|
|
SXG_RING_ADVANCE_TAIL(_ringinfo); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
*
|
|
|
|
|
* Host Command Buffer - commands to INIC via the Cmd Rings
|
|
|
|
|
*
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
/*
|
|
|
|
|
* 31 15 0
|
|
|
|
|
* .___________________.___________________.
|
|
|
|
|
* |<-------------- Sgl Low -------------->|
|
|
|
|
|
* |_________|_________|_________|_________|0 0x00
|
|
|
|
|
* |<-------------- Sgl High ------------->|
|
|
|
|
|
* |_________|_________|_________|_________|4 0x04
|
|
|
|
|
* |<------------- Sge 0 Low ----------->|
|
|
|
|
|
* |_________|_________|_________|_________|8 0x08
|
|
|
|
|
* |<------------- Sge 0 High ----------->|
|
|
|
|
|
* |_________|_________|_________|_________|12 0x0c
|
|
|
|
|
* |<------------ Sge 0 Length ---------->|
|
|
|
|
|
* |_________|_________|_________|_________|16 0x10
|
|
|
|
|
* |<----------- Window Update ----------->|
|
|
|
|
|
* |<-------- SP 1st SGE offset ---------->|
|
|
|
|
|
* |_________|_________|_________|_________|20 0x14
|
|
|
|
|
* |<----------- Total Length ------------>|
|
|
|
|
|
* |_________|_________|_________|_________|24 0x18
|
|
|
|
|
* |<----- LCnt ------>|<----- Flags ----->|
|
|
|
|
|
* |_________|_________|_________|_________|28 0x1c
|
|
|
|
|
*/
|
|
|
|
|
#pragma pack(push, 1)
|
|
|
|
|
typedef struct _SXG_CMD {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
dma_addr_t Sgl; // Physical address of SGL
|
2008-08-21 21:04:55 +00:00
|
|
|
|
union {
|
|
|
|
|
struct {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
dma64_addr_t FirstSgeAddress; // Address of first SGE
|
|
|
|
|
u32 FirstSgeLength; // Length of first SGE
|
2008-08-21 21:04:55 +00:00
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
u32 Rsvd1; // TOE NA
|
|
|
|
|
u32 SgeOffset; // Slowpath - 2nd SGE offset
|
|
|
|
|
u32 Resid; // MDL completion - clobbers update
|
2008-08-21 21:04:55 +00:00
|
|
|
|
};
|
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
u32 TotalLength; // Total transfer length
|
|
|
|
|
u32 Mss; // LSO MSS
|
2008-08-21 21:04:55 +00:00
|
|
|
|
};
|
|
|
|
|
} Buffer;
|
|
|
|
|
};
|
|
|
|
|
union {
|
|
|
|
|
struct {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
unsigned char Flags:4; // slowpath flags
|
|
|
|
|
unsigned char IpHl:4; // Ip header length (>>2)
|
|
|
|
|
unsigned char MacLen; // Mac header len
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} CsumFlags;
|
|
|
|
|
struct {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort Flags:4; // slowpath flags
|
|
|
|
|
ushort TcpHdrOff:7; // TCP
|
|
|
|
|
ushort MacLen:5; // Mac header len
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} LsoFlags;
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort Flags; // flags
|
2008-08-21 21:04:55 +00:00
|
|
|
|
};
|
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort SgEntries; // SG entry count including first sge
|
2008-08-21 21:04:55 +00:00
|
|
|
|
struct {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
unsigned char Status; // Copied from event status
|
|
|
|
|
unsigned char NotUsed;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} Status;
|
|
|
|
|
};
|
|
|
|
|
} SXG_CMD, *PSXG_CMD;
|
|
|
|
|
#pragma pack(pop)
|
|
|
|
|
|
|
|
|
|
#pragma pack(push, 1)
|
|
|
|
|
typedef struct _VLAN_HDR {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
ushort VlanTci;
|
|
|
|
|
ushort VlanTpid;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} VLAN_HDR, *PVLAN_HDR;
|
|
|
|
|
#pragma pack(pop)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Slowpath Flags:
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* LSS Flags:
|
|
|
|
|
* .---
|
|
|
|
|
* /.--- TCP Large segment send
|
|
|
|
|
* //.---
|
|
|
|
|
* ///.---
|
|
|
|
|
* 3 1 1 ////
|
|
|
|
|
* 1 5 0 ||||
|
|
|
|
|
* .___________________.____________vvvv.
|
|
|
|
|
* | |MAC | TCP | |
|
|
|
|
|
* | LCnt |hlen|hdroff|Flgs|
|
|
|
|
|
* |___________________|||||||||||||____|
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* Checksum Flags
|
|
|
|
|
*
|
|
|
|
|
* .---
|
|
|
|
|
* /.---
|
|
|
|
|
* //.--- Checksum TCP
|
|
|
|
|
* ///.--- Checksum IP
|
|
|
|
|
* 3 1 //// No bits - normal send
|
|
|
|
|
* 1 5 7 ||||
|
|
|
|
|
* .___________________._______________vvvv.
|
|
|
|
|
* | | Offload | IP | |
|
|
|
|
|
* | LCnt |MAC hlen |Hlen|Flgs|
|
|
|
|
|
* |___________________|____|____|____|____|
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
// Slowpath CMD flags
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP
|
|
|
|
|
#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP
|
|
|
|
|
#define SXG_SLOWCMD_LSO 0x04 // Large segment send
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
|
|
typedef struct _SXG_XMT_RING {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_XMT_RING, *PSXG_XMT_RING;
|
|
|
|
|
|
|
|
|
|
typedef struct _SXG_RCV_RING {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_RING, *PSXG_RCV_RING;
|
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
* Share memory buffer types - Used to identify asynchronous
|
|
|
|
|
* shared memory allocation
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
typedef enum {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_BUFFER_TYPE_RCV, // Receive buffer
|
|
|
|
|
SXG_BUFFER_TYPE_SGL // SGL buffer
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_BUFFER_TYPE;
|
|
|
|
|
|
|
|
|
|
// State for SXG buffers
|
|
|
|
|
#define SXG_BUFFER_FREE 0x01
|
|
|
|
|
#define SXG_BUFFER_BUSY 0x02
|
|
|
|
|
#define SXG_BUFFER_ONCARD 0x04
|
|
|
|
|
#define SXG_BUFFER_UPSTREAM 0x08
|
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
* Receive data buffers
|
|
|
|
|
*
|
|
|
|
|
* Receive data buffers are given to the Sahara card 128 at a time.
|
|
|
|
|
* This is accomplished by filling in a "receive descriptor block"
|
|
|
|
|
* with 128 "receive descriptors". Each descriptor consists of
|
|
|
|
|
* a physical address, which the card uses as the address to
|
|
|
|
|
* DMA data into, and a virtual address, which is given back
|
|
|
|
|
* to the host in the "HostHandle" portion of an event.
|
|
|
|
|
* The receive descriptor data structure is defined below
|
|
|
|
|
* as SXG_RCV_DATA_DESCRIPTOR, and the corresponding block
|
|
|
|
|
* is defined as SXG_RCV_DESCRIPTOR_BLOCK.
|
|
|
|
|
*
|
|
|
|
|
* This receive descriptor block is given to the card by filling
|
|
|
|
|
* in the Sgl field of a SXG_CMD entry from pAdapt->RcvRings[0]
|
|
|
|
|
* with the physical address of the receive descriptor block.
|
|
|
|
|
*
|
|
|
|
|
* Both the receive buffers and the receive descriptor blocks
|
|
|
|
|
* require additional data structures to maintain them
|
|
|
|
|
* on a free queue and contain other information associated with them.
|
|
|
|
|
* Those data structures are defined as the SXG_RCV_DATA_BUFFER_HDR
|
|
|
|
|
* and SXG_RCV_DESCRIPTOR_BLOCK_HDR respectively.
|
|
|
|
|
*
|
|
|
|
|
* Since both the receive buffers and the receive descriptor block
|
|
|
|
|
* must be accessible by the card, both must be allocated out of
|
|
|
|
|
* shared memory. To ensure that we always have a descriptor
|
|
|
|
|
* block available for every 128 buffers, we allocate all of
|
|
|
|
|
* these resources together in a single block. This entire
|
|
|
|
|
* block is managed by a SXG_RCV_BLOCK_HDR, who's sole purpose
|
|
|
|
|
* is to maintain address information so that the entire block
|
|
|
|
|
* can be free later.
|
|
|
|
|
*
|
|
|
|
|
* Further complicating matters is the fact that the receive
|
|
|
|
|
* buffers must be variable in length in order to accomodate
|
|
|
|
|
* jumbo frame configurations. We configure the buffer
|
|
|
|
|
* length so that the buffer and it's corresponding SXG_RCV_DATA_BUFFER_HDR
|
|
|
|
|
* structure add up to an even boundary. Then we place the
|
|
|
|
|
* remaining data structures after 128 of them as shown in
|
|
|
|
|
* the following diagram:
|
|
|
|
|
*
|
|
|
|
|
* _________________________________________
|
|
|
|
|
* | |
|
|
|
|
|
* | Variable length receive buffer #1 |
|
|
|
|
|
* |_________________________________________|
|
|
|
|
|
* | |
|
|
|
|
|
* | SXG_RCV_DATA_BUFFER_HDR #1 |
|
|
|
|
|
* |_________________________________________| <== Even 2k or 10k boundary
|
|
|
|
|
* | |
|
|
|
|
|
* | ... repeat 2-128 .. |
|
|
|
|
|
* |_________________________________________|
|
|
|
|
|
* | |
|
|
|
|
|
* | SXG_RCV_DESCRIPTOR_BLOCK |
|
|
|
|
|
* | Contains SXG_RCV_DATA_DESCRIPTOR * 128 |
|
|
|
|
|
* |_________________________________________|
|
|
|
|
|
* | |
|
|
|
|
|
* | SXG_RCV_DESCRIPTOR_BLOCK_HDR |
|
|
|
|
|
* |_________________________________________|
|
|
|
|
|
* | |
|
|
|
|
|
* | SXG_RCV_BLOCK_HDR |
|
|
|
|
|
* |_________________________________________|
|
|
|
|
|
*
|
|
|
|
|
* Memory consumption:
|
|
|
|
|
* Non-jumbo:
|
|
|
|
|
* Buffers and SXG_RCV_DATA_BUFFER_HDR = 2k * 128 = 256k
|
|
|
|
|
* + SXG_RCV_DESCRIPTOR_BLOCK = 2k
|
|
|
|
|
* + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
|
|
|
|
|
* + SXG_RCV_BLOCK_HDR = ~32
|
|
|
|
|
* => Total = ~258k/block
|
|
|
|
|
*
|
|
|
|
|
* Jumbo:
|
|
|
|
|
* Buffers and SXG_RCV_DATA_BUFFER_HDR = 10k * 128 = 1280k
|
|
|
|
|
* + SXG_RCV_DESCRIPTOR_BLOCK = 2k
|
|
|
|
|
* + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
|
|
|
|
|
* + SXG_RCV_BLOCK_HDR = ~32
|
|
|
|
|
* => Total = ~1282k/block
|
|
|
|
|
*
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card
|
|
|
|
|
#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers
|
|
|
|
|
#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
|
|
// Receive buffer header
|
|
|
|
|
typedef struct _SXG_RCV_DATA_BUFFER_HDR {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
dma_addr_t PhysicalAddress; // Buffer physical address
|
2008-08-21 21:04:55 +00:00
|
|
|
|
// Note - DO NOT USE the VirtualAddress field to locate data.
|
|
|
|
|
// Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
|
2008-10-14 22:00:15 +00:00
|
|
|
|
void *VirtualAddress; // Start of buffer
|
|
|
|
|
LIST_ENTRY FreeList; // Free queue of buffers
|
|
|
|
|
struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
|
|
|
|
|
u32 Size; // Buffer size
|
|
|
|
|
u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
|
|
|
|
|
unsigned char State; // See SXG_BUFFER state above
|
|
|
|
|
unsigned char Status; // Event status (to log PUSH)
|
|
|
|
|
struct sk_buff *skb; // Double mapped (nbl and pkt)
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
|
|
|
|
|
|
|
|
|
|
// SxgSlowReceive uses the PACKET (skb) contained
|
|
|
|
|
// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
|
|
|
|
|
#define SxgDumbRcvPacket skb
|
|
|
|
|
|
2008-10-14 22:00:15 +00:00
|
|
|
|
#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR
|
2008-08-21 21:04:55 +00:00
|
|
|
|
#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR
|
|
|
|
|
#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
|
|
|
|
|
|
|
|
|
|
// Receive data descriptor
|
|
|
|
|
typedef struct _SXG_RCV_DATA_DESCRIPTOR {
|
|
|
|
|
union {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
struct sk_buff *VirtualAddress; // Host handle
|
|
|
|
|
u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
|
2008-08-21 21:04:55 +00:00
|
|
|
|
};
|
2008-10-14 22:00:15 +00:00
|
|
|
|
dma_addr_t PhysicalAddress;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
|
|
|
|
|
|
|
|
|
|
// Receive descriptor block
|
|
|
|
|
#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
|
|
|
|
|
#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
|
|
|
|
|
typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
|
|
|
|
|
|
|
|
|
|
// Receive descriptor block header
|
|
|
|
|
typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
void *VirtualAddress; // Start of 2k buffer
|
|
|
|
|
dma_addr_t PhysicalAddress; // ..and it's physical address
|
|
|
|
|
LIST_ENTRY FreeList; // Free queue of descriptor blocks
|
|
|
|
|
unsigned char State; // See SXG_BUFFER state above
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
|
|
|
|
|
|
|
|
|
|
// Receive block header
|
|
|
|
|
typedef struct _SXG_RCV_BLOCK_HDR {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
void *VirtualAddress; // Start of virtual memory
|
|
|
|
|
dma_addr_t PhysicalAddress; // ..and it's physical address
|
|
|
|
|
LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
|
|
|
|
|
|
|
|
|
|
// Macros to determine data structure offsets into receive block
|
|
|
|
|
#define SXG_RCV_BLOCK_SIZE(_Buffersize) \
|
|
|
|
|
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
|
|
|
|
|
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
|
|
|
|
|
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)) + \
|
|
|
|
|
(sizeof(SXG_RCV_BLOCK_HDR)))
|
|
|
|
|
#define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize) \
|
|
|
|
|
((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
|
|
|
|
|
#define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize) \
|
|
|
|
|
((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
|
|
|
|
|
#define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize) \
|
|
|
|
|
((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
|
|
|
|
|
#define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
|
|
|
|
|
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
|
|
|
|
|
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)))
|
|
|
|
|
#define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize) \
|
|
|
|
|
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
|
|
|
|
|
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
|
|
|
|
|
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
|
|
|
|
|
|
|
|
|
|
// Use the miniport reserved portion of the NBL to locate
|
|
|
|
|
// our SXG_RCV_DATA_BUFFER_HDR structure.
|
|
|
|
|
typedef struct _SXG_RCV_NBL_RESERVED {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
|
|
|
|
|
void *Available;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
|
|
|
|
|
|
|
|
|
|
#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
|
|
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
|
|
|
* Scatter gather list buffer
|
|
|
|
|
***************************************************************************/
|
|
|
|
|
#define SXG_INITIAL_SGL_BUFFERS 8192 // Initial pool of SGL buffers
|
|
|
|
|
#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
|
|
|
|
|
#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
|
|
|
|
|
|
|
|
|
|
// Self identifying structure type
|
|
|
|
|
typedef enum _SXG_SGL_TYPE {
|
2008-10-14 22:00:15 +00:00
|
|
|
|
SXG_SGL_DUMB, // Dumb NIC SGL
|
|
|
|
|
SXG_SGL_SLOW, // Slowpath protocol header - see below
|
|
|
|
|
SXG_SGL_CHIMNEY // Chimney offload SGL
|
2008-08-21 21:04:55 +00:00
|
|
|
|
} SXG_SGL_TYPE, PSXG_SGL_TYPE;
|
|
|
|
|
|
|
|
|
|
// Note - the description below is Microsoft specific
|
|
|
|
|
//
|
|
|
|
|
// The following definition specifies the amount of shared memory to allocate
|
|
|
|
|
// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
|
|
|
|
|
// The following considerations apply when setting this value:
|
|
|
|
|
// - First, the Sahara card is designed to read the Microsoft SGL structure
|
2008-10-14 22:00:15 +00:00
|
|
|
|
// straight out of host memory. This means that the SGL must reside in
|
|
|
|
|
// shared memory. If the length here is smaller than the SGL for the
|
|
|
|
|
// NET_BUFFER, then NDIS will allocate its own buffer. The buffer
|
|
|
|
|
// that NDIS allocates is not in shared memory, so when this happens,
|
|
|
|
|
// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
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// In other words.. we don't want this value to be too small.
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2008-08-21 21:04:55 +00:00
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// - On the other hand.. we're allocating up to 16k of these things. If
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2008-10-14 22:00:15 +00:00
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// we make this too big, we start to consume a ton of memory..
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2008-08-21 21:04:55 +00:00
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// At the moment, I'm going to limit the number of SG entries to 150.
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// If each entry maps roughly 4k, then this should cover roughly 600kB
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// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total
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// SGE portion of the structure consumes 3600 bytes, which should allow
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// the entire SXG_SCATTER_GATHER structure to reside comfortably within
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// a 4k block, providing the remaining fields stay under 500 bytes.
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//
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// So with 150 entries, the SXG_SCATTER_GATHER structure becomes roughly
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// 4k. At 16k of them, that amounts to 64M of shared memory. A ton, but
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// manageable.
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#define SXG_SGL_ENTRIES 150
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// The ucode expects an NDIS SGL structure that
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// is formatted for an x64 system. When running
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// on an x64 system, we can simply hand the NDIS SGL
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// to the card directly. For x86 systems we must reconstruct
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// the SGL. The following structure defines an x64
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// formatted SGL entry
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typedef struct _SXG_X64_SGE {
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2008-10-14 22:00:15 +00:00
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dma64_addr_t Address; // same as wdm.h
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u32 Length; // same as wdm.h
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u32 CompilerPad; // The compiler pads to 8-bytes
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u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
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2008-08-21 21:04:55 +00:00
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} SXG_X64_SGE, *PSXG_X64_SGE;
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typedef struct _SCATTER_GATHER_ELEMENT {
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2008-10-14 22:00:15 +00:00
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dma64_addr_t Address; // same as wdm.h
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u32 Length; // same as wdm.h
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u32 CompilerPad; // The compiler pads to 8-bytes
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u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
|
2008-08-21 21:04:55 +00:00
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} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
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typedef struct _SCATTER_GATHER_LIST {
|
2008-10-14 22:00:15 +00:00
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u32 NumberOfElements;
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u32 *Reserved;
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SCATTER_GATHER_ELEMENT Elements[];
|
2008-08-21 21:04:55 +00:00
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} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
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// The card doesn't care about anything except elements, so
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// we can leave the u32 * reserved field alone in the following
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// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
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// we can specify SXG_X64_SGE and define a fixed number of elements
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typedef struct _SXG_X64_SGL {
|
2008-10-14 22:00:15 +00:00
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u32 NumberOfElements;
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|
u32 *Reserved;
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|
SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
|
2008-08-21 21:04:55 +00:00
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|
} SXG_X64_SGL, *PSXG_X64_SGL;
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|
typedef struct _SXG_SCATTER_GATHER {
|
2008-10-14 22:00:15 +00:00
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SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
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void *adapter; // Back pointer to adapter
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LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
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|
LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
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|
dma_addr_t PhysicalAddress; // physical address
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unsigned char State; // See SXG_BUFFER state above
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|
unsigned char CmdIndex; // Command ring index
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|
|
struct sk_buff *DumbPacket; // Associated Packet
|
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|
u32 Direction; // For asynchronous completions
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|
u32 CurOffset; // Current SGL offset
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|
u32 SglRef; // SGL reference count
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|
|
VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
|
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|
|
PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl
|
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|
|
SXG_X64_SGL Sgl; // SGL handed to card
|
2008-08-21 21:04:55 +00:00
|
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|
|
} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
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|
|
#if defined(CONFIG_X86_64)
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|
|
#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
|
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|
|
|
#define SXG_SGL_BUF_SIZE sizeof(SXG_X64_SGL)
|
|
|
|
|
#elif defined(CONFIG_X86)
|
|
|
|
|
// Force NDIS to give us it's own buffer so we can reformat to our own
|
|
|
|
|
#define SXG_SGL_BUFFER(_SxgSgl) NULL
|
|
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|
|
#define SXG_SGL_BUF_SIZE 0
|
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|
|
#else
|
2008-10-14 22:00:15 +00:00
|
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|
|
Stop Compilation;
|
2008-08-21 21:04:55 +00:00
|
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|
|
#endif
|