2010-07-02 22:25:03 +00:00
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/*
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* P1022DS board specific routines
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*
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* Authors: Travis Wheatley <travis.wheatley@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is taken from the Freescale P1022DS BSP, with modifications:
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* 2) No AMP support
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* 3) No PCI endpoint support
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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2010-08-31 16:39:25 +00:00
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#include <linux/memblock.h>
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2010-10-07 09:36:43 +00:00
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#include <asm/div64.h>
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2010-07-02 22:25:03 +00:00
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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2010-10-07 09:36:43 +00:00
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#include <asm/fsl_guts.h>
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/*
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* Board-specific initialization of the DIU. This code should probably be
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* executed when the DIU is opened, rather than in arch code, but the DIU
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* driver does not have a mechanism for this (yet).
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*
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* This is especially problematic on the P1022DS because the local bus (eLBC)
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* and the DIU video signals share the same pins, which means that enabling the
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* DIU will disable access to NOR flash.
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*/
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/* Some ngPIXIS register definitions */
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PX_BRDCFG1_DDCEN 0x10
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_MASK 0x0E000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_MASK 0x01800000
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_MASK 0x00600000
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_MASK 0x00180000
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#define AD_RED_C_SHIFT 19
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#define AD_PALETTE 0x00040000
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#define AD_PIXEL_S_MASK 0x00030000
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_MASK 0x0000F000
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_MASK 0x00000F00
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_MASK 0x000000F0
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_MASK 0x0000000F
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#define AD_COMP_0_SHIFT 0
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#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
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(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
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(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
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(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
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/**
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* p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
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*
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* The Area Descriptor is a 32-bit value that determine which bits in each
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* pixel are to be used for each color.
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*/
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2011-07-09 20:38:14 +00:00
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static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
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unsigned int bits_per_pixel)
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2010-10-07 09:36:43 +00:00
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{
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switch (bits_per_pixel) {
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case 32:
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/* 0x88883316 */
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return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
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case 24:
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/* 0x88082219 */
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return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
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case 16:
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/* 0x65053118 */
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return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
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default:
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pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
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return 0;
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}
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}
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/**
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* p1022ds_set_gamma_table: update the gamma table, if necessary
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*
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* On some boards, the gamma table for some ports may need to be modified.
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* This is not the case on the P1022DS, so we do nothing.
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*/
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2011-07-09 20:38:14 +00:00
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static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
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char *gamma_table_base)
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2010-10-07 09:36:43 +00:00
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{
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}
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/**
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* p1022ds_set_monitor_port: switch the output to a different monitor port
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*
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*/
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2011-07-09 20:38:14 +00:00
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static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
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2010-10-07 09:36:43 +00:00
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{
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powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards. There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis". Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.
We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed. This means that older kernels are
not compatible with newer device trees. This is not a real problem, however,
since that particular function doesn't work anyway. When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-15 18:04:13 +00:00
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struct device_node *np;
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2011-06-08 20:01:57 +00:00
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void __iomem *pixis;
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2010-10-07 09:36:43 +00:00
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u8 __iomem *brdcfg1;
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powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards. There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis". Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.
We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed. This means that older kernels are
not compatible with newer device trees. This is not a real problem, however,
since that particular function doesn't work anyway. When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-15 18:04:13 +00:00
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np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
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if (!np)
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/* older device trees used "fsl,p1022ds-pixis" */
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np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
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if (!np) {
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2010-10-07 09:36:43 +00:00
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pr_err("p1022ds: missing ngPIXIS node\n");
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return;
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}
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powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards. There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis". Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.
We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed. This means that older kernels are
not compatible with newer device trees. This is not a real problem, however,
since that particular function doesn't work anyway. When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-15 18:04:13 +00:00
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pixis = of_iomap(np, 0);
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2011-06-08 20:01:57 +00:00
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if (!pixis) {
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2010-10-07 09:36:43 +00:00
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pr_err("p1022ds: could not map ngPIXIS registers\n");
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return;
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}
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2011-06-08 20:01:57 +00:00
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brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
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2010-10-07 09:36:43 +00:00
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2011-07-09 20:38:14 +00:00
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switch (port) {
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case FSL_DIU_PORT_DVI:
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printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
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2010-10-07 09:36:43 +00:00
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/* Enable the DVI port, disable the DFP and the backlight */
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clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
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PX_BRDCFG1_DVIEN);
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break;
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2011-07-09 20:38:14 +00:00
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case FSL_DIU_PORT_LVDS:
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printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
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2010-10-07 09:36:43 +00:00
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/* Enable the DFP port, disable the DVI and the backlight */
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clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
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PX_BRDCFG1_DFPEN);
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break;
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default:
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2011-07-09 20:38:14 +00:00
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pr_err("p1022ds: unsupported monitor port %i\n", port);
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2010-10-07 09:36:43 +00:00
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}
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2011-06-08 20:01:57 +00:00
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iounmap(pixis);
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2010-10-07 09:36:43 +00:00
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}
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/**
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* p1022ds_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022ds_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts_85xx __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022ds: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022ds: could not map global utilties device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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2011-06-23 19:48:54 +00:00
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the CLKDVDR register, and the valid
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* range of values is 2-255.
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*/
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2010-10-07 09:36:43 +00:00
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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2011-06-23 19:48:54 +00:00
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pxclk = clamp_t(u32, pxclk, 2, 255);
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2010-10-07 09:36:43 +00:00
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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2011-06-08 20:01:57 +00:00
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iounmap(guts);
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2010-10-07 09:36:43 +00:00
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}
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/**
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2011-07-09 20:38:14 +00:00
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* p1022ds_valid_monitor_port: set the monitor port for sysfs
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2010-10-07 09:36:43 +00:00
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*/
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2011-07-09 20:38:14 +00:00
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enum fsl_diu_monitor_port
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p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
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2010-10-07 09:36:43 +00:00
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{
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2011-07-09 20:38:14 +00:00
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switch (port) {
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case FSL_DIU_PORT_DVI:
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case FSL_DIU_PORT_LVDS:
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return port;
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default:
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return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
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}
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2010-10-07 09:36:43 +00:00
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}
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#endif
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2010-07-02 22:25:03 +00:00
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void __init p1022_ds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np;
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np = of_find_node_by_type(NULL, "open-pic");
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if (!np) {
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pr_err("Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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pr_err("Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET |
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MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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}
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#ifdef CONFIG_SMP
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void __init mpc85xx_smp_init(void);
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#endif
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/*
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* Setup the architecture
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*/
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static void __init p1022_ds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("p1022_ds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
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struct resource rsrc;
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struct pci_controller *hose;
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|
|
|
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|
of_address_to_resource(np, 0, &rsrc);
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|
|
|
|
|
|
|
if ((rsrc.start & 0xfffff) == 0x8000)
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|
|
|
fsl_add_bridge(np, 1);
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|
|
|
else
|
|
|
|
fsl_add_bridge(np, 0);
|
|
|
|
|
|
|
|
hose = pci_find_hose_for_OF_device(np);
|
|
|
|
max = min(max, hose->dma_window_base_cur +
|
|
|
|
hose->dma_window_size);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-10-07 09:36:43 +00:00
|
|
|
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
|
|
|
diu_ops.get_pixel_format = p1022ds_get_pixel_format;
|
|
|
|
diu_ops.set_gamma_table = p1022ds_set_gamma_table;
|
|
|
|
diu_ops.set_monitor_port = p1022ds_set_monitor_port;
|
|
|
|
diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
|
2011-07-09 20:38:14 +00:00
|
|
|
diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
|
2010-10-07 09:36:43 +00:00
|
|
|
#endif
|
|
|
|
|
2010-07-02 22:25:03 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
mpc85xx_smp_init();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
2010-08-31 16:39:25 +00:00
|
|
|
if (memblock_end_of_DRAM() > max) {
|
2010-07-02 22:25:03 +00:00
|
|
|
ppc_swiotlb_enable = 1;
|
|
|
|
set_pci_dma_ops(&swiotlb_dma_ops);
|
|
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
pr_info("Freescale P1022 DS reference board\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct of_device_id __initdata p1022_ds_ids[] = {
|
|
|
|
{ .type = "soc", },
|
|
|
|
{ .compatible = "soc", },
|
|
|
|
{ .compatible = "simple-bus", },
|
|
|
|
{ .compatible = "gianfar", },
|
2010-08-19 21:28:12 +00:00
|
|
|
/* So that the DMA channel nodes can be probed individually: */
|
|
|
|
{ .compatible = "fsl,eloplus-dma", },
|
2010-07-02 22:25:03 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init p1022_ds_publish_devices(void)
|
|
|
|
{
|
|
|
|
return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
|
|
|
|
}
|
|
|
|
machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
|
|
|
|
|
|
|
|
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Called very early, device-tree isn't unflattened
|
|
|
|
*/
|
|
|
|
static int __init p1022_ds_probe(void)
|
|
|
|
{
|
|
|
|
unsigned long root = of_get_flat_dt_root();
|
|
|
|
|
|
|
|
return of_flat_dt_is_compatible(root, "fsl,p1022ds");
|
|
|
|
}
|
|
|
|
|
|
|
|
define_machine(p1022_ds) {
|
|
|
|
.name = "P1022 DS",
|
|
|
|
.probe = p1022_ds_probe,
|
|
|
|
.setup_arch = p1022_ds_setup_arch,
|
|
|
|
.init_IRQ = p1022_ds_pic_init,
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
|
|
|
#endif
|
|
|
|
.get_irq = mpic_get_irq,
|
|
|
|
.restart = fsl_rstcr_restart,
|
|
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
|
|
.progress = udbg_progress,
|
|
|
|
};
|