linux/drivers/ata/sata_promise.c

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/*
* sata_promise.c - Promise SATA
*
* Maintained by: Jeff Garzik <jgarzik@pobox.com>
* Mikael Pettersson <mikpe@it.uu.se>
* Please ALWAYS copy linux-ide@vger.kernel.org
* on emails.
*
* Copyright 2003-2004 Red Hat, Inc.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* libata documentation is available via 'make {ps|pdf}docs',
* as Documentation/DocBook/libata.*
*
* Hardware information only available under NDA.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <linux/libata.h>
#include "sata_promise.h"
#define DRV_NAME "sata_promise"
#define DRV_VERSION "2.12"
enum {
PDC_MAX_PORTS = 4,
PDC_MMIO_BAR = 3,
PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
/* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
PDC_FLASH_CTL = 0x44, /* Flash control register */
PDC_PCI_CTL = 0x48, /* PCI control/status reg */
PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
/* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
/* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
PDC_SATA_ERROR = 0x04,
PDC_PHYMODE4 = 0x14,
PDC_LINK_LAYER_ERRORS = 0x6C,
PDC_FPDMA_CTLSTAT = 0xD8,
PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
/* PDC_FPDMA_CTLSTAT bit definitions */
PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
/* PDC_GLOBAL_CTL bit definitions */
PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
PDC_DRIVE_ERR = (1 << 21), /* drive error */
PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
PDC2_ATA_DMA_CNT_ERR,
PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
PDC1_ERR_MASK | PDC2_ERR_MASK,
board_2037x = 0, /* FastTrak S150 TX2plus */
board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
board_20319 = 2, /* FastTrak S150 TX4 */
board_20619 = 3, /* FastTrak TX4000 */
board_2057x = 4, /* SATAII150 Tx2plus */
board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
board_40518 = 6, /* SATAII150 Tx4 */
PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
/* Sequence counter control registers bit definitions */
PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
/* Feature register values */
PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
/* Device/Head register values */
PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
/* PDC_CTLSTAT bit definitions */
PDC_DMA_ENABLE = (1 << 7),
PDC_IRQ_DISABLE = (1 << 10),
PDC_RESET = (1 << 11), /* HDMA reset */
PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
/* ap->flags bits */
PDC_FLAG_GEN_II = (1 << 24),
PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
};
struct pdc_port_priv {
u8 *pkt;
dma_addr_t pkt_dma;
};
static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int pdc_common_port_start(struct ata_port *ap);
static int pdc_sata_port_start(struct ata_port *ap);
static void pdc_qc_prep(struct ata_queued_cmd *qc);
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
static void pdc_irq_clear(struct ata_port *ap);
static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_freeze(struct ata_port *ap);
static void pdc_sata_freeze(struct ata_port *ap);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_thaw(struct ata_port *ap);
static void pdc_sata_thaw(struct ata_port *ap);
static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
unsigned long deadline);
static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline);
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:50 +00:00
static void pdc_error_handler(struct ata_port *ap);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
static int pdc_pata_cable_detect(struct ata_port *ap);
static int pdc_sata_cable_detect(struct ata_port *ap);
static struct scsi_host_template pdc_ata_sht = {
ATA_BASE_SHT(DRV_NAME),
.sg_tablesize = PDC_MAX_PRD,
.dma_boundary = ATA_DMA_BOUNDARY,
};
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
static const struct ata_port_operations pdc_common_ops = {
.inherits = &ata_sff_port_ops,
.sff_tf_load = pdc_tf_load_mmio,
.sff_exec_command = pdc_exec_command_mmio,
.check_atapi_dma = pdc_check_atapi_dma,
.qc_prep = pdc_qc_prep,
.qc_issue = pdc_qc_issue,
.sff_irq_clear = pdc_irq_clear,
.lost_interrupt = ATA_OP_NULL,
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
.post_internal_cmd = pdc_post_internal_cmd,
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:50 +00:00
.error_handler = pdc_error_handler,
};
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
static struct ata_port_operations pdc_sata_ops = {
.inherits = &pdc_common_ops,
.cable_detect = pdc_sata_cable_detect,
.freeze = pdc_sata_freeze,
.thaw = pdc_sata_thaw,
.scr_read = pdc_sata_scr_read,
.scr_write = pdc_sata_scr_write,
.port_start = pdc_sata_port_start,
.hardreset = pdc_sata_hardreset,
};
/* First-generation chips need a more restrictive ->check_atapi_dma op,
and ->freeze/thaw that ignore the hotplug controls. */
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
static struct ata_port_operations pdc_old_sata_ops = {
.inherits = &pdc_sata_ops,
.freeze = pdc_freeze,
.thaw = pdc_thaw,
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
.check_atapi_dma = pdc_old_sata_check_atapi_dma,
};
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
static struct ata_port_operations pdc_pata_ops = {
.inherits = &pdc_common_ops,
.cable_detect = pdc_pata_cable_detect,
.freeze = pdc_freeze,
.thaw = pdc_thaw,
.port_start = pdc_common_port_start,
.softreset = pdc_pata_softreset,
};
static const struct ata_port_info pdc_port_info[] = {
[board_2037x] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
PDC_FLAG_SATA_PATA,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_old_sata_ops,
},
[board_2037x_pata] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_pata_ops,
},
[board_20319] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
PDC_FLAG_4_PORTS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_old_sata_ops,
},
[board_20619] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
PDC_FLAG_4_PORTS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_pata_ops,
},
2006-01-17 13:06:21 +00:00
[board_2057x] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_sata_ops,
},
[board_2057x_pata] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
PDC_FLAG_GEN_II,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_pata_ops,
},
[board_40518] =
{
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &pdc_sata_ops,
},
};
static const struct pci_device_id pdc_ata_pci_tbl[] = {
{ PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
{ PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
{ PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
{ PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
{ PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
{ PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
{ PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
{ PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
{ PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
{ PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
{ PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
{ PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
{ PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
{ PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
{ PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
{ PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
{ PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
{ } /* terminate list */
};
static struct pci_driver pdc_ata_pci_driver = {
.name = DRV_NAME,
.id_table = pdc_ata_pci_tbl,
.probe = pdc_ata_init_one,
.remove = ata_pci_remove_one,
};
static int pdc_common_port_start(struct ata_port *ap)
{
struct device *dev = ap->host->dev;
struct pdc_port_priv *pp;
int rc;
libata-sff: clean up BMDMA initialization When BMDMA initialization failed or BMDMA was not available for whatever reason, bmdma_addr was left at zero and used as an indication that BMDMA shouldn't be used. This leads to the following problems. p1. For BMDMA drivers which don't use traditional BMDMA register, ata_bmdma_mode_filter() incorrectly inhibits DMA modes. Those drivers either have to inherit from ata_sff_port_ops or clear ->mode_filter explicitly. p2. non-BMDMA drivers call into BMDMA PRD table allocation. It doesn't actually allocate PRD table if bmdma_addr is not initialized but is still confusing. p3. For BMDMA drivers which don't use traditional BMDMA register, some methods might not be invoked as expected (e.g. bmdma_stop from ata_sff_post_internal_cmd()). p4. SFF drivers w/ custom DMA interface implement noop BMDMA ops worrying libata core might call into one of them. These problems are caused by the muddy line between SFF and BMDMA and the assumption that all BMDMA controllers initialize bmdma_addr. This patch fixes p1 and p2 by removing the bmdma_addr assumption and moving prd allocation to BMDMA port start. Later patches will fix the remaining issues. This patch improves BMDMA initialization such that * When BMDMA register initialization fails, falls back to PIO instead of failing. ata_pci_bmdma_init() never fails now. * When ata_pci_bmdma_init() falls back to PIO, it clears ap->mwdma_mask and udma_mask instead of depending on ata_bmdma_mode_filter(). This makes ata_bmdma_mode_filter() unnecessary thus resolving p1. * ata_port_start() which actually is BMDMA specific is moved to ata_bmdma_port_start(). ata_port_start() and ata_sff_port_start() are killed. * ata_sff_port_start32() is moved and renamed to ata_bmdma_port_start32(). Drivers which no longer call into PRD table allocation are... pdc_adma, sata_inic162x, sata_qstor, sata_sx4, pata_cmd640 and all drivers which inherit from ata_sff_port_ops. pata_icside sets ->port_start to ATA_OP_NULL as it doesn't need PRD but is a BMDMA controller and doesn't have custom port_start like other such controllers. Note that with the previous patch which makes all and only BMDMA drivers inherit from ata_bmdma_port_ops, this change doesn't break drivers which need PRD table. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-05-10 19:41:34 +00:00
/* we use the same prd table as bmdma, allocate it */
rc = ata_bmdma_port_start(ap);
if (rc)
return rc;
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
if (!pp)
return -ENOMEM;
pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
if (!pp->pkt)
return -ENOMEM;
ap->private_data = pp;
return 0;
}
static int pdc_sata_port_start(struct ata_port *ap)
{
int rc;
rc = pdc_common_port_start(ap);
if (rc)
return rc;
/* fix up PHYMODE4 align timing */
if (ap->flags & PDC_FLAG_GEN_II) {
void __iomem *sata_mmio = ap->ioaddr.scr_addr;
unsigned int tmp;
tmp = readl(sata_mmio + PDC_PHYMODE4);
tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
writel(tmp, sata_mmio + PDC_PHYMODE4);
}
return 0;
}
static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
{
void __iomem *sata_mmio = ap->ioaddr.scr_addr;
u32 tmp;
tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
/* It's not allowed to write to the entire FPDMA_CTLSTAT register
when NCQ is running. So do a byte-sized write to bits 10 and 11. */
writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
}
static void pdc_fpdma_reset(struct ata_port *ap)
{
void __iomem *sata_mmio = ap->ioaddr.scr_addr;
u8 tmp;
tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
tmp &= 0x7F;
tmp |= PDC_FPDMA_CTLSTAT_RESET;
writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
udelay(100);
tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
pdc_fpdma_clear_interrupt_flag(ap);
}
static void pdc_not_at_command_packet_phase(struct ata_port *ap)
{
void __iomem *sata_mmio = ap->ioaddr.scr_addr;
unsigned int i;
u32 tmp;
/* check not at ASIC packet command phase */
for (i = 0; i < 100; ++i) {
writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
if ((tmp & 0xF) != 1)
break;
udelay(100);
}
}
static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
{
void __iomem *sata_mmio = ap->ioaddr.scr_addr;
writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
}
static void pdc_reset_port(struct ata_port *ap)
{
void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
unsigned int i;
u32 tmp;
if (ap->flags & PDC_FLAG_GEN_II)
pdc_not_at_command_packet_phase(ap);
tmp = readl(ata_ctlstat_mmio);
tmp |= PDC_RESET;
writel(tmp, ata_ctlstat_mmio);
for (i = 11; i > 0; i--) {
tmp = readl(ata_ctlstat_mmio);
if (tmp & PDC_RESET)
break;
udelay(100);
tmp |= PDC_RESET;
writel(tmp, ata_ctlstat_mmio);
}
tmp &= ~PDC_RESET;
writel(tmp, ata_ctlstat_mmio);
readl(ata_ctlstat_mmio); /* flush */
if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
pdc_fpdma_reset(ap);
pdc_clear_internal_debug_record_error_register(ap);
}
}
static int pdc_pata_cable_detect(struct ata_port *ap)
{
u8 tmp;
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
if (tmp & 0x01)
return ATA_CBL_PATA40;
return ATA_CBL_PATA80;
}
static int pdc_sata_cable_detect(struct ata_port *ap)
{
return ATA_CBL_SATA;
}
static int pdc_sata_scr_read(struct ata_link *link,
unsigned int sc_reg, u32 *val)
{
if (sc_reg > SCR_CONTROL)
return -EINVAL;
*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
return 0;
}
static int pdc_sata_scr_write(struct ata_link *link,
unsigned int sc_reg, u32 val)
{
if (sc_reg > SCR_CONTROL)
return -EINVAL;
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
return 0;
}
static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
dma_addr_t sg_table = ap->bmdma_prd_dma;
unsigned int cdb_len = qc->dev->cdb_len;
u8 *cdb = qc->cdb;
struct pdc_port_priv *pp = ap->private_data;
u8 *buf = pp->pkt;
__le32 *buf32 = (__le32 *) buf;
unsigned int dev_sel, feature;
/* set control bits (byte 0), zero delay seq id (byte 3),
* and seq id (byte 2)
*/
switch (qc->tf.protocol) {
case ATAPI_PROT_DMA:
if (!(qc->tf.flags & ATA_TFLAG_WRITE))
buf32[0] = cpu_to_le32(PDC_PKT_READ);
else
buf32[0] = 0;
break;
case ATAPI_PROT_NODATA:
buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
break;
default:
BUG();
break;
}
buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
buf32[2] = 0; /* no next-packet */
/* select drive */
if (sata_scr_valid(&ap->link))
dev_sel = PDC_DEVICE_SATA;
else
dev_sel = qc->tf.device;
buf[12] = (1 << 5) | ATA_REG_DEVICE;
buf[13] = dev_sel;
buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
buf[15] = dev_sel; /* once more, waiting for BSY to clear */
buf[16] = (1 << 5) | ATA_REG_NSECT;
buf[17] = qc->tf.nsect;
buf[18] = (1 << 5) | ATA_REG_LBAL;
buf[19] = qc->tf.lbal;
/* set feature and byte counter registers */
if (qc->tf.protocol != ATAPI_PROT_DMA)
feature = PDC_FEATURE_ATAPI_PIO;
else
feature = PDC_FEATURE_ATAPI_DMA;
buf[20] = (1 << 5) | ATA_REG_FEATURE;
buf[21] = feature;
buf[22] = (1 << 5) | ATA_REG_BYTEL;
buf[23] = qc->tf.lbam;
buf[24] = (1 << 5) | ATA_REG_BYTEH;
buf[25] = qc->tf.lbah;
/* send ATAPI packet command 0xA0 */
buf[26] = (1 << 5) | ATA_REG_CMD;
buf[27] = qc->tf.command;
/* select drive and check DRQ */
buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
buf[29] = dev_sel;
/* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
BUG_ON(cdb_len & ~0x1E);
/* append the CDB as the final part */
buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
memcpy(buf+31, cdb, cdb_len);
}
/**
* pdc_fill_sg - Fill PCI IDE PRD table
* @qc: Metadata associated with taskfile to be transferred
*
* Fill PCI IDE PRD (scatter-gather) table with segments
* associated with the current disk command.
* Make sure hardware does not choke on it.
*
* LOCKING:
* spin_lock_irqsave(host lock)
*
*/
static void pdc_fill_sg(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct ata_bmdma_prd *prd = ap->bmdma_prd;
struct scatterlist *sg;
const u32 SG_COUNT_ASIC_BUG = 41*4;
unsigned int si, idx;
u32 len;
if (!(qc->flags & ATA_QCFLAG_DMAMAP))
return;
idx = 0;
for_each_sg(qc->sg, sg, qc->n_elem, si) {
u32 addr, offset;
u32 sg_len;
/* determine if physical DMA addr spans 64K boundary.
* Note h/w doesn't support 64-bit, so we unconditionally
* truncate dma_addr_t to u32.
*/
addr = (u32) sg_dma_address(sg);
sg_len = sg_dma_len(sg);
while (sg_len) {
offset = addr & 0xffff;
len = sg_len;
if ((offset + sg_len) > 0x10000)
len = 0x10000 - offset;
prd[idx].addr = cpu_to_le32(addr);
prd[idx].flags_len = cpu_to_le32(len & 0xffff);
VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
idx++;
sg_len -= len;
addr += len;
}
}
len = le32_to_cpu(prd[idx - 1].flags_len);
if (len > SG_COUNT_ASIC_BUG) {
u32 addr;
VPRINTK("Splitting last PRD.\n");
addr = le32_to_cpu(prd[idx - 1].addr);
prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
addr = addr + len - SG_COUNT_ASIC_BUG;
len = SG_COUNT_ASIC_BUG;
prd[idx].addr = cpu_to_le32(addr);
prd[idx].flags_len = cpu_to_le32(len);
VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
idx++;
}
prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
}
static void pdc_qc_prep(struct ata_queued_cmd *qc)
{
struct pdc_port_priv *pp = qc->ap->private_data;
unsigned int i;
VPRINTK("ENTER\n");
switch (qc->tf.protocol) {
case ATA_PROT_DMA:
pdc_fill_sg(qc);
/*FALLTHROUGH*/
case ATA_PROT_NODATA:
i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
qc->dev->devno, pp->pkt);
if (qc->tf.flags & ATA_TFLAG_LBA48)
i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
else
i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
pdc_pkt_footer(&qc->tf, pp->pkt, i);
break;
case ATAPI_PROT_PIO:
pdc_fill_sg(qc);
break;
case ATAPI_PROT_DMA:
pdc_fill_sg(qc);
/*FALLTHROUGH*/
case ATAPI_PROT_NODATA:
pdc_atapi_pkt(qc);
break;
default:
break;
}
}
static int pdc_is_sataii_tx4(unsigned long flags)
{
const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
return (flags & mask) == mask;
}
static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
int is_sataii_tx4)
{
static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
}
static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
{
return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
}
static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
{
const struct ata_host *host = ap->host;
unsigned int nr_ports = pdc_sata_nr_ports(ap);
unsigned int i;
for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
;
BUG_ON(i >= nr_ports);
return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
}
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_freeze(struct ata_port *ap)
{
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
u32 tmp;
tmp = readl(ata_mmio + PDC_CTLSTAT);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
tmp |= PDC_IRQ_DISABLE;
tmp &= ~PDC_DMA_ENABLE;
writel(tmp, ata_mmio + PDC_CTLSTAT);
readl(ata_mmio + PDC_CTLSTAT); /* flush */
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
}
static void pdc_sata_freeze(struct ata_port *ap)
{
struct ata_host *host = ap->host;
void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
u32 hotplug_status;
/* Disable hotplug events on this port.
*
* Locking:
* 1) hotplug register accesses must be serialised via host->lock
* 2) ap->lock == &ap->host->lock
* 3) ->freeze() and ->thaw() are called with ap->lock held
*/
hotplug_status = readl(host_mmio + hotplug_offset);
hotplug_status |= 0x11 << (ata_no + 16);
writel(hotplug_status, host_mmio + hotplug_offset);
readl(host_mmio + hotplug_offset); /* flush */
pdc_freeze(ap);
}
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_thaw(struct ata_port *ap)
{
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
u32 tmp;
/* clear IRQ */
readl(ata_mmio + PDC_COMMAND);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
/* turn IRQ back on */
tmp = readl(ata_mmio + PDC_CTLSTAT);
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
tmp &= ~PDC_IRQ_DISABLE;
writel(tmp, ata_mmio + PDC_CTLSTAT);
readl(ata_mmio + PDC_CTLSTAT); /* flush */
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
}
static void pdc_sata_thaw(struct ata_port *ap)
{
struct ata_host *host = ap->host;
void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
u32 hotplug_status;
pdc_thaw(ap);
/* Enable hotplug events on this port.
* Locking: see pdc_sata_freeze().
*/
hotplug_status = readl(host_mmio + hotplug_offset);
hotplug_status |= 0x11 << ata_no;
hotplug_status &= ~(0x11 << (ata_no + 16));
writel(hotplug_status, host_mmio + hotplug_offset);
readl(host_mmio + hotplug_offset); /* flush */
}
static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
unsigned long deadline)
{
pdc_reset_port(link->ap);
return ata_sff_softreset(link, class, deadline);
}
static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
{
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
/* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
return (ata_mmio - host_mmio - 0x200) / 0x80;
}
static void pdc_hard_reset_port(struct ata_port *ap)
{
void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
u8 tmp;
spin_lock(&ap->host->lock);
tmp = readb(pcictl_b1_mmio);
tmp &= ~(0x10 << ata_no);
writeb(tmp, pcictl_b1_mmio);
readb(pcictl_b1_mmio); /* flush */
udelay(100);
tmp |= (0x10 << ata_no);
writeb(tmp, pcictl_b1_mmio);
readb(pcictl_b1_mmio); /* flush */
spin_unlock(&ap->host->lock);
}
static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline)
{
if (link->ap->flags & PDC_FLAG_GEN_II)
pdc_not_at_command_packet_phase(link->ap);
/* hotplug IRQs should have been masked by pdc_sata_freeze() */
pdc_hard_reset_port(link->ap);
pdc_reset_port(link->ap);
/* sata_promise can't reliably acquire the first D2H Reg FIS
* after hardreset. Do non-waiting hardreset and request
* follow-up SRST.
*/
return sata_std_hardreset(link, class, deadline);
}
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:50 +00:00
static void pdc_error_handler(struct ata_port *ap)
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
{
if (!(ap->pflags & ATA_PFLAG_FROZEN))
pdc_reset_port(ap);
ata_sff_error_handler(ap);
}
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
/* make DMA engine forget about the failed command */
if (qc->flags & ATA_QCFLAG_FAILED)
[PATCH] sata_promise: new EH conversion, take 2 This patch converts sata_promise to use new-style libata error handling on Promise SATA chips, for both SATA and PATA ports. * ATA_FLAG_SRST is no longer set * ->phy_reset is no longer set as it is unused when ->error_handler is present, and pdc_sata_phy_reset() has been removed * pdc_freeze() masks interrupts and halts DMA via PDC_CTLSTAT * pdc_thaw() clears interrupt status in PDC_INT_SEQMASK and then unmasks interrupts in PDC_CTLSTAT * pdc_error_handler() reinitialises the port if it isn't frozen, and then invokes ata_do_eh() with standard {s,}ata reset methods * pdc_post_internal_cmd() resets the port in case of errors * the PATA-only 20619 chip continues to use old-style EH: not by necessity but simply because I don't have documentation for it or any way to test it Since the previous version pdc_error_handler() has been rewritten and it now mostly matches ahci and sata_sil24. In case anyone wonders: the call to pdc_reset_port() isn't a heavy-duty reset, it's a light-weight reset to quickly put a port into a sane state. The discussion about the PCI flushes in pdc_freeze() and pdc_thaw() seemed to end with a consensus that the flushes are OK and not obviously redundant, so I decided to keep them for now. This patch was prepared against 2.6.19-git7, but it also applies to 2.6.19 + libata #upstream, with or without the revised sata_promise cleanup patch I recently submitted. This patch does conflict with the #promise-sata-pata patch: this patch removes pdc_sata_phy_reset() while #promise-sata-pata modifies it. The correct patch resolution is to remove the function. Tested on 2037x and 2057x chips, with PATA patches on top and disks on both SATA and PATA ports. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-12-06 23:06:51 +00:00
pdc_reset_port(ap);
}
static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
u32 port_status, u32 err_mask)
{
struct ata_eh_info *ehi = &ap->link.eh_info;
unsigned int ac_err_mask = 0;
ata_ehi_clear_desc(ehi);
ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
port_status &= err_mask;
if (port_status & PDC_DRIVE_ERR)
ac_err_mask |= AC_ERR_DEV;
if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
ac_err_mask |= AC_ERR_OTHER;
if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
ac_err_mask |= AC_ERR_ATA_BUS;
if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
| PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
ac_err_mask |= AC_ERR_HOST_BUS;
if (sata_scr_valid(&ap->link)) {
u32 serror;
pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
ehi->serror |= serror;
}
qc->err_mask |= ac_err_mask;
pdc_reset_port(ap);
ata_port_abort(ap);
}
static unsigned int pdc_host_intr(struct ata_port *ap,
struct ata_queued_cmd *qc)
{
unsigned int handled = 0;
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
u32 port_status, err_mask;
err_mask = PDC_ERR_MASK;
if (ap->flags & PDC_FLAG_GEN_II)
err_mask &= ~PDC1_ERR_MASK;
else
err_mask &= ~PDC2_ERR_MASK;
port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
if (unlikely(port_status & err_mask)) {
pdc_error_intr(ap, qc, port_status, err_mask);
return 1;
}
switch (qc->tf.protocol) {
case ATA_PROT_DMA:
case ATA_PROT_NODATA:
case ATAPI_PROT_DMA:
case ATAPI_PROT_NODATA:
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
ata_qc_complete(qc);
handled = 1;
break;
default:
ap->stats.idle_irq++;
break;
}
return handled;
}
static void pdc_irq_clear(struct ata_port *ap)
{
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
readl(ata_mmio + PDC_COMMAND);
}
static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
{
struct ata_host *host = dev_instance;
struct ata_port *ap;
u32 mask = 0;
unsigned int i, tmp;
unsigned int handled = 0;
void __iomem *host_mmio;
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
unsigned int hotplug_offset, ata_no;
u32 hotplug_status;
int is_sataii_tx4;
VPRINTK("ENTER\n");
if (!host || !host->iomap[PDC_MMIO_BAR]) {
VPRINTK("QUICK EXIT\n");
return IRQ_NONE;
}
host_mmio = host->iomap[PDC_MMIO_BAR];
spin_lock(&host->lock);
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
/* read and clear hotplug flags for all ports */
if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
hotplug_offset = PDC2_SATA_PLUG_CSR;
hotplug_status = readl(host_mmio + hotplug_offset);
if (hotplug_status & 0xff)
writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
hotplug_status &= 0xff; /* clear uninteresting bits */
} else
hotplug_status = 0;
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
/* reading should also clear interrupts */
mask = readl(host_mmio + PDC_INT_SEQMASK);
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
if (mask == 0xffffffff && hotplug_status == 0) {
VPRINTK("QUICK EXIT 2\n");
goto done_irq;
}
mask &= 0xffff; /* only 16 SEQIDs possible */
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
if (mask == 0 && hotplug_status == 0) {
VPRINTK("QUICK EXIT 3\n");
goto done_irq;
}
writel(mask, host_mmio + PDC_INT_SEQMASK);
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
for (i = 0; i < host->n_ports; i++) {
VPRINTK("port %u\n", i);
ap = host->ports[i];
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
/* check for a plug or unplug event */
ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
tmp = hotplug_status & (0x11 << ata_no);
if (tmp) {
struct ata_eh_info *ehi = &ap->link.eh_info;
sata_promise: SATA hotplug support, take 2 This patch enables hotplugging of SATA devices in the sata_promise driver. It's been tested successfully on both first- and second-generation Promise SATA chips: SATA150 TX2plus, SATAII150 TX2plus, SATAII150 TX4, SATA300 TX2plus, and SATA300 TX4. The only quirk I've seen is that hotplugging (insertion) on the first-generation SATA150 TX2plus requires a lengthier EH sequence than on the second-generation chips. On the second-generation chips a simple soft reset seems to suffice, but on the first-generation chip there's a "port is slow to respond" after the initial soft reset, after which libata issues a hard reset, and then the device is recognised. The hotplug checks are high up in the interrupt handling path, not deep down in error_intr as in ahci/sata_sil24. That's because the chip doesn't signal hotplug status changes in the per-port status register: instead a global register contains hotplug control and status flags for all ports. I considered following the ahci/sata_sil24 structure, but that would have required non-trivial changes to the interrupt handling path, so I chose to keep the hotplug changes simple and unobtrusive. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> -- This patch depends on the "sata_promise: cleanups" patch. Changes since the previous version (posted June 19): - Correct pdc_interrupt() to increment 'handled' also in the hotplug case. This prevents IRQ_NONE from being returned when an interrupt only has hotplug events to handle, which could confuse the kernel's IRQ machinery. - Added testing on the SATAII150 TX4. drivers/ata/sata_promise.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-02 23:09:05 +00:00
ata_ehi_clear_desc(ehi);
ata_ehi_hotplugged(ehi);
ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
ata_port_freeze(ap);
++handled;
continue;
}
/* check for a packet interrupt */
tmp = mask & (1 << (i + 1));
if (tmp) {
struct ata_queued_cmd *qc;
qc = ata_qc_from_tag(ap, ap->link.active_tag);
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
handled += pdc_host_intr(ap, qc);
}
}
VPRINTK("EXIT\n");
done_irq:
spin_unlock(&host->lock);
return IRQ_RETVAL(handled);
}
static void pdc_packet_start(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct pdc_port_priv *pp = ap->private_data;
void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
unsigned int port_no = ap->port_no;
u8 seq = (u8) (port_no + 1);
VPRINTK("ENTER, ap %p\n", ap);
writel(0x00000001, host_mmio + (seq * 4));
readl(host_mmio + (seq * 4)); /* flush */
pp->pkt[2] = seq;
wmb(); /* flush PRD, pkt writes */
writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
}
static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
{
switch (qc->tf.protocol) {
case ATAPI_PROT_NODATA:
if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
break;
/*FALLTHROUGH*/
case ATA_PROT_NODATA:
if (qc->tf.flags & ATA_TFLAG_POLLING)
break;
/*FALLTHROUGH*/
case ATAPI_PROT_DMA:
case ATA_PROT_DMA:
pdc_packet_start(qc);
return 0;
default:
break;
}
return ata_sff_qc_issue(qc);
}
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
{
WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
ata_sff_tf_load(ap, tf);
}
static void pdc_exec_command_mmio(struct ata_port *ap,
const struct ata_taskfile *tf)
{
WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
ata_sff_exec_command(ap, tf);
}
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
{
u8 *scsicmd = qc->scsicmd->cmnd;
int pio = 1; /* atapi dma off by default */
/* Whitelist commands that may use DMA. */
switch (scsicmd[0]) {
case WRITE_12:
case WRITE_10:
case WRITE_6:
case READ_12:
case READ_10:
case READ_6:
case 0xad: /* READ_DVD_STRUCTURE */
case 0xbe: /* READ_CD */
pio = 0;
}
/* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
if (scsicmd[0] == WRITE_10) {
unsigned int lba =
(scsicmd[2] << 24) |
(scsicmd[3] << 16) |
(scsicmd[4] << 8) |
scsicmd[5];
if (lba >= 0xFFFF4FA2)
pio = 1;
}
return pio;
}
static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
/* First generation chips cannot use ATAPI DMA on SATA ports */
return 1;
}
static void pdc_ata_setup_port(struct ata_port *ap,
void __iomem *base, void __iomem *scr_addr)
{
ap->ioaddr.cmd_addr = base;
ap->ioaddr.data_addr = base;
ap->ioaddr.feature_addr =
ap->ioaddr.error_addr = base + 0x4;
ap->ioaddr.nsect_addr = base + 0x8;
ap->ioaddr.lbal_addr = base + 0xc;
ap->ioaddr.lbam_addr = base + 0x10;
ap->ioaddr.lbah_addr = base + 0x14;
ap->ioaddr.device_addr = base + 0x18;
ap->ioaddr.command_addr =
ap->ioaddr.status_addr = base + 0x1c;
ap->ioaddr.altstatus_addr =
ap->ioaddr.ctl_addr = base + 0x38;
ap->ioaddr.scr_addr = scr_addr;
}
static void pdc_host_init(struct ata_host *host)
{
void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
int hotplug_offset;
u32 tmp;
if (is_gen2)
hotplug_offset = PDC2_SATA_PLUG_CSR;
else
hotplug_offset = PDC_SATA_PLUG_CSR;
/*
* Except for the hotplug stuff, this is voodoo from the
* Promise driver. Label this entire section
* "TODO: figure out why we do this"
*/
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
/* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
tmp = readl(host_mmio + PDC_FLASH_CTL);
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
tmp |= 0x02000; /* bit 13 (enable bmr burst) */
if (!is_gen2)
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
writel(tmp, host_mmio + PDC_FLASH_CTL);
/* clear plug/unplug flags for all ports */
tmp = readl(host_mmio + hotplug_offset);
writel(tmp | 0xff, host_mmio + hotplug_offset);
tmp = readl(host_mmio + hotplug_offset);
if (is_gen2) /* unmask plug/unplug ints */
writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
else /* mask plug/unplug ints */
writel(tmp | 0xff0000, host_mmio + hotplug_offset);
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
/* don't initialise TBG or SLEW on 2nd generation chips */
if (is_gen2)
[PATCH] sata_promise fixes and updates This patch updates the sata_promise driver as follows: - Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41 in first-generation chips. This error caused PCI access alignment exceptions on SPARC64, and on all platforms it disabled the expected initialisation of TBG mode. - Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II and use it to distinguish first- and second-generation chips. - Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second- generation chips. This matches Promises' ulsata2 driver. - Prevent TBG mode and SLEW rate initialisation in second-generation chips. These two registers have moved, TBG mode has been redefined, and Promise's ulsata2 driver no longer attempts to initialise them. - Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are marked as 2057x (2nd gen) not 2037x (1st gen). - Correct PCI device table so device 0x3d17 is marked as 40518 (2nd gen 4 ports) not 20319 (1st gen 4 ports). - Correct pdc_ata_init_one() to treat 20771 as a second-generation chip. Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips. The information comes from the newly uploaded Promise SATA HW specs, Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips. hp->hotplug_offset could now be removed and its value recomputed in pdc_host_init() using hp->flags, but that would be a cleanup not a functional change, so I'm ignoring it for now. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 21:00:15 +00:00
return;
/* reduce TBG clock to 133 Mhz. */
tmp = readl(host_mmio + PDC_TBG_MODE);
tmp &= ~0x30000; /* clear bit 17, 16*/
tmp |= 0x10000; /* set bit 17:16 = 0:1 */
writel(tmp, host_mmio + PDC_TBG_MODE);
readl(host_mmio + PDC_TBG_MODE); /* flush */
msleep(10);
/* adjust slew rate control register. */
tmp = readl(host_mmio + PDC_SLEW_CTL);
tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
writel(tmp, host_mmio + PDC_SLEW_CTL);
}
static int pdc_ata_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
const struct ata_port_info *ppi[PDC_MAX_PORTS];
struct ata_host *host;
void __iomem *host_mmio;
int n_ports, i, rc;
int is_sataii_tx4;
ata_print_version_once(&pdev->dev, DRV_VERSION);
/* enable and acquire resources */
rc = pcim_enable_device(pdev);
if (rc)
return rc;
rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
if (rc == -EBUSY)
pcim_pin_device(pdev);
if (rc)
return rc;
host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
/* determine port configuration and setup host */
n_ports = 2;
if (pi->flags & PDC_FLAG_4_PORTS)
n_ports = 4;
for (i = 0; i < n_ports; i++)
ppi[i] = pi;
if (pi->flags & PDC_FLAG_SATA_PATA) {
u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
if (!(tmp & 0x80))
ppi[n_ports++] = pi + 1;
}
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
if (!host) {
dev_err(&pdev->dev, "failed to allocate host\n");
return -ENOMEM;
}
host->iomap = pcim_iomap_table(pdev);
is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
for (i = 0; i < host->n_ports; i++) {
struct ata_port *ap = host->ports[i];
unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
unsigned int ata_offset = 0x200 + ata_no * 0x80;
unsigned int scr_offset = 0x400 + ata_no * 0x100;
pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
}
/* initialize adapter */
pdc_host_init(host);
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
if (rc)
return rc;
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
if (rc)
return rc;
/* start host, request IRQ and attach */
pci_set_master(pdev);
return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
&pdc_ata_sht);
}
static int __init pdc_ata_init(void)
{
return pci_register_driver(&pdc_ata_pci_driver);
}
static void __exit pdc_ata_exit(void)
{
pci_unregister_driver(&pdc_ata_pci_driver);
}
MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
module_init(pdc_ata_init);
module_exit(pdc_ata_exit);