2009-06-05 12:42:42 +00:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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2009-09-08 00:10:24 +00:00
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#include <linux/firmware.h>
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#include <linux/platform_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-06-05 12:42:42 +00:00
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#include "drmP.h"
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#include "radeon.h"
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2010-03-11 21:19:17 +00:00
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#include "radeon_asic.h"
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2009-09-18 08:41:24 +00:00
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#include "radeon_drm.h"
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2009-09-08 00:10:24 +00:00
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#include "rv770d.h"
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#include "atom.h"
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2009-09-28 16:34:43 +00:00
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#include "avivod.h"
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2009-06-05 12:42:42 +00:00
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2009-09-08 00:10:24 +00:00
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#define R700_PFP_UCODE_SIZE 848
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#define R700_PM4_UCODE_SIZE 1360
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2009-06-05 12:42:42 +00:00
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2009-09-08 00:10:24 +00:00
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static void rv770_gpu_init(struct radeon_device *rdev);
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void rv770_fini(struct radeon_device *rdev);
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2009-06-05 12:42:42 +00:00
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2010-04-23 21:57:27 +00:00
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void rv770_pm_misc(struct radeon_device *rdev)
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{
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2010-05-28 23:35:01 +00:00
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int requested_index = rdev->pm.requested_power_state_index;
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struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
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struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
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2010-04-23 21:57:27 +00:00
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2010-05-28 23:35:01 +00:00
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if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
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radeon_atom_set_voltage(rdev, voltage->voltage);
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2010-04-23 21:57:27 +00:00
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}
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2009-06-05 12:42:42 +00:00
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/*
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2009-09-08 00:10:24 +00:00
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* GART
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2009-06-05 12:42:42 +00:00
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*/
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2009-09-08 00:10:24 +00:00
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int rv770_pcie_gart_enable(struct radeon_device *rdev)
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2009-06-05 12:42:42 +00:00
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{
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2009-09-08 00:10:24 +00:00
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u32 tmp;
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int r, i;
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2009-06-05 12:42:42 +00:00
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2009-09-14 16:29:49 +00:00
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if (rdev->gart.table.vram.robj == NULL) {
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dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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2009-09-08 00:10:24 +00:00
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}
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2009-09-14 16:29:49 +00:00
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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2009-09-08 00:10:24 +00:00
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return r;
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2010-02-05 06:00:07 +00:00
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radeon_gart_restore(rdev);
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2009-09-08 00:10:24 +00:00
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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EFFECTIVE_L2_QUEUE_SIZE(7));
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WREG32(VM_L2_CNTL2, 0);
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WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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/* Setup TLB control */
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tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
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SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
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EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
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2009-10-06 17:04:30 +00:00
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WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
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2009-09-08 00:10:24 +00:00
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
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WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
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WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
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(u32)(rdev->dummy_page.addr >> 12));
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for (i = 1; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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2009-06-05 12:42:42 +00:00
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2009-09-08 00:10:24 +00:00
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r600_pcie_gart_tlb_flush(rdev);
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rdev->gart.ready = true;
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2009-06-05 12:42:42 +00:00
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return 0;
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}
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2009-09-08 00:10:24 +00:00
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void rv770_pcie_gart_disable(struct radeon_device *rdev)
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2009-06-05 12:42:42 +00:00
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{
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2009-09-08 00:10:24 +00:00
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u32 tmp;
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2009-11-20 13:29:23 +00:00
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int i, r;
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2009-09-08 00:10:24 +00:00
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/* Disable all tables */
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for (i = 0; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
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EFFECTIVE_L2_QUEUE_SIZE(7));
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WREG32(VM_L2_CNTL2, 0);
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WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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/* Setup TLB control */
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tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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2009-09-14 16:29:49 +00:00
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if (rdev->gart.table.vram.robj) {
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2009-11-20 13:29:23 +00:00
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r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(rdev->gart.table.vram.robj);
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radeon_bo_unpin(rdev->gart.table.vram.robj);
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radeon_bo_unreserve(rdev->gart.table.vram.robj);
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}
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2009-09-14 16:29:49 +00:00
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}
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}
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void rv770_pcie_gart_fini(struct radeon_device *rdev)
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{
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2010-03-17 14:44:29 +00:00
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radeon_gart_fini(rdev);
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2009-09-14 16:29:49 +00:00
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rv770_pcie_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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2009-06-05 12:42:42 +00:00
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}
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2009-10-06 17:04:30 +00:00
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void rv770_agp_enable(struct radeon_device *rdev)
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{
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u32 tmp;
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int i;
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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EFFECTIVE_L2_QUEUE_SIZE(7));
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WREG32(VM_L2_CNTL2, 0);
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WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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/* Setup TLB control */
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tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
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SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
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EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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for (i = 0; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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}
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2009-10-01 16:02:13 +00:00
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static void rv770_mc_program(struct radeon_device *rdev)
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2009-06-05 12:42:42 +00:00
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{
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2009-10-01 16:02:13 +00:00
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struct rv515_mc_save save;
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2009-09-08 00:10:24 +00:00
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u32 tmp;
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int i, j;
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/* Initialize HDP */
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for (i = 0, j = 0; i < 32; i++, j += 0x18) {
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WREG32((0x2c14 + j), 0x00000000);
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WREG32((0x2c18 + j), 0x00000000);
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WREG32((0x2c1c + j), 0x00000000);
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WREG32((0x2c20 + j), 0x00000000);
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WREG32((0x2c24 + j), 0x00000000);
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}
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WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
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2009-10-01 16:02:13 +00:00
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rv515_mc_stop(rdev, &save);
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2009-09-08 00:10:24 +00:00
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if (r600_mc_wait_for_idle(rdev)) {
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2009-10-01 16:02:13 +00:00
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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2009-09-08 00:10:24 +00:00
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}
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/* Lockout access through VGA aperture*/
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WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
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/* Update configuration */
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2009-10-06 17:04:30 +00:00
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if (rdev->flags & RADEON_IS_AGP) {
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if (rdev->mc.vram_start < rdev->mc.gtt_start) {
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/* VRAM before AGP */
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WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
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rdev->mc.vram_start >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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rdev->mc.gtt_end >> 12);
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} else {
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/* VRAM after AGP */
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WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
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rdev->mc.gtt_start >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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rdev->mc.vram_end >> 12);
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}
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} else {
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WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
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rdev->mc.vram_start >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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rdev->mc.vram_end >> 12);
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}
|
2009-09-08 00:10:24 +00:00
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
|
2009-10-06 17:04:30 +00:00
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tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
|
2009-09-08 00:10:24 +00:00
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tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(MC_VM_FB_LOCATION, tmp);
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WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
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WREG32(HDP_NONSURFACE_INFO, (2 << 7));
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WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
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if (rdev->flags & RADEON_IS_AGP) {
|
2009-10-06 17:04:30 +00:00
|
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WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
|
2009-09-08 00:10:24 +00:00
|
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WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
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WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
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} else {
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|
|
WREG32(MC_VM_AGP_BASE, 0);
|
|
|
|
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
|
|
|
|
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
|
|
|
|
}
|
|
|
|
if (r600_mc_wait_for_idle(rdev)) {
|
2009-10-01 16:02:13 +00:00
|
|
|
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
2009-09-08 00:10:24 +00:00
|
|
|
}
|
2009-10-01 16:02:13 +00:00
|
|
|
rv515_mc_resume(rdev, &save);
|
2009-09-18 04:16:38 +00:00
|
|
|
/* we need to own VRAM, so turn off the VGA renderer here
|
|
|
|
* to stop it overwriting our objects */
|
2009-09-28 16:34:43 +00:00
|
|
|
rv515_vga_render_disable(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* CP.
|
|
|
|
*/
|
|
|
|
void r700_cp_stop(struct radeon_device *rdev)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
2009-09-08 00:10:24 +00:00
|
|
|
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
static int rv770_cp_load_microcode(struct radeon_device *rdev)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
2009-09-08 00:10:24 +00:00
|
|
|
const __be32 *fw_data;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!rdev->me_fw || !rdev->pfp_fw)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
r700_cp_stop(rdev);
|
|
|
|
WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
|
|
|
|
|
|
|
|
/* Reset cp */
|
|
|
|
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
|
|
|
|
RREG32(GRBM_SOFT_RESET);
|
|
|
|
mdelay(15);
|
|
|
|
WREG32(GRBM_SOFT_RESET, 0);
|
|
|
|
|
|
|
|
fw_data = (const __be32 *)rdev->pfp_fw->data;
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
|
|
|
|
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
|
|
|
|
fw_data = (const __be32 *)rdev->me_fw->data;
|
|
|
|
WREG32(CP_ME_RAM_WADDR, 0);
|
|
|
|
for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
|
|
|
|
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
|
|
|
|
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
WREG32(CP_ME_RAM_WADDR, 0);
|
|
|
|
WREG32(CP_ME_RAM_RADDR, 0);
|
|
|
|
return 0;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
2010-03-24 17:36:43 +00:00
|
|
|
void r700_cp_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
r700_cp_stop(rdev);
|
|
|
|
radeon_ring_fini(rdev);
|
|
|
|
}
|
2009-06-05 12:42:42 +00:00
|
|
|
|
|
|
|
/*
|
2009-09-08 00:10:24 +00:00
|
|
|
* Core functions
|
2009-06-05 12:42:42 +00:00
|
|
|
*/
|
2010-02-19 21:22:31 +00:00
|
|
|
static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
|
|
|
u32 num_tile_pipes,
|
|
|
|
u32 num_backends,
|
|
|
|
u32 backend_disable_mask)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
2009-09-08 00:10:24 +00:00
|
|
|
u32 backend_map = 0;
|
|
|
|
u32 enabled_backends_mask;
|
|
|
|
u32 enabled_backends_count;
|
|
|
|
u32 cur_pipe;
|
|
|
|
u32 swizzle_pipe[R7XX_MAX_PIPES];
|
|
|
|
u32 cur_backend;
|
|
|
|
u32 i;
|
2010-02-19 21:22:31 +00:00
|
|
|
bool force_no_swizzle;
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
if (num_tile_pipes > R7XX_MAX_PIPES)
|
|
|
|
num_tile_pipes = R7XX_MAX_PIPES;
|
|
|
|
if (num_tile_pipes < 1)
|
|
|
|
num_tile_pipes = 1;
|
|
|
|
if (num_backends > R7XX_MAX_BACKENDS)
|
|
|
|
num_backends = R7XX_MAX_BACKENDS;
|
|
|
|
if (num_backends < 1)
|
|
|
|
num_backends = 1;
|
|
|
|
|
|
|
|
enabled_backends_mask = 0;
|
|
|
|
enabled_backends_count = 0;
|
|
|
|
for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
|
|
|
|
if (((backend_disable_mask >> i) & 1) == 0) {
|
|
|
|
enabled_backends_mask |= (1 << i);
|
|
|
|
++enabled_backends_count;
|
|
|
|
}
|
|
|
|
if (enabled_backends_count == num_backends)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enabled_backends_count == 0) {
|
|
|
|
enabled_backends_mask = 1;
|
|
|
|
enabled_backends_count = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enabled_backends_count != num_backends)
|
|
|
|
num_backends = enabled_backends_count;
|
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_RV770:
|
|
|
|
case CHIP_RV730:
|
|
|
|
force_no_swizzle = false;
|
|
|
|
break;
|
|
|
|
case CHIP_RV710:
|
|
|
|
case CHIP_RV740:
|
|
|
|
default:
|
|
|
|
force_no_swizzle = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
|
|
|
|
switch (num_tile_pipes) {
|
|
|
|
case 1:
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 1;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
swizzle_pipe[3] = 3;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 3;
|
|
|
|
swizzle_pipe[3] = 1;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
swizzle_pipe[3] = 3;
|
|
|
|
swizzle_pipe[4] = 4;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 4;
|
|
|
|
swizzle_pipe[3] = 1;
|
|
|
|
swizzle_pipe[4] = 3;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
swizzle_pipe[3] = 3;
|
|
|
|
swizzle_pipe[4] = 4;
|
|
|
|
swizzle_pipe[5] = 5;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 4;
|
|
|
|
swizzle_pipe[3] = 5;
|
|
|
|
swizzle_pipe[4] = 3;
|
|
|
|
swizzle_pipe[5] = 1;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
swizzle_pipe[3] = 3;
|
|
|
|
swizzle_pipe[4] = 4;
|
|
|
|
swizzle_pipe[5] = 5;
|
|
|
|
swizzle_pipe[6] = 6;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 4;
|
|
|
|
swizzle_pipe[3] = 6;
|
|
|
|
swizzle_pipe[4] = 3;
|
|
|
|
swizzle_pipe[5] = 1;
|
|
|
|
swizzle_pipe[6] = 5;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
case 8:
|
2010-02-19 21:22:31 +00:00
|
|
|
if (force_no_swizzle) {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 1;
|
|
|
|
swizzle_pipe[2] = 2;
|
|
|
|
swizzle_pipe[3] = 3;
|
|
|
|
swizzle_pipe[4] = 4;
|
|
|
|
swizzle_pipe[5] = 5;
|
|
|
|
swizzle_pipe[6] = 6;
|
|
|
|
swizzle_pipe[7] = 7;
|
|
|
|
} else {
|
|
|
|
swizzle_pipe[0] = 0;
|
|
|
|
swizzle_pipe[1] = 2;
|
|
|
|
swizzle_pipe[2] = 4;
|
|
|
|
swizzle_pipe[3] = 6;
|
|
|
|
swizzle_pipe[4] = 3;
|
|
|
|
swizzle_pipe[5] = 1;
|
|
|
|
swizzle_pipe[6] = 7;
|
|
|
|
swizzle_pipe[7] = 5;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
cur_backend = 0;
|
|
|
|
for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
|
|
|
|
while (((1 << cur_backend) & enabled_backends_mask) == 0)
|
|
|
|
cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
|
|
|
|
|
|
|
|
backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
|
|
|
|
|
|
|
|
cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return backend_map;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
static void rv770_gpu_init(struct radeon_device *rdev)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
2009-09-08 00:10:24 +00:00
|
|
|
int i, j, num_qd_pipes;
|
2010-02-19 21:22:31 +00:00
|
|
|
u32 ta_aux_cntl;
|
2009-09-08 00:10:24 +00:00
|
|
|
u32 sx_debug_1;
|
|
|
|
u32 smx_dc_ctl0;
|
2010-02-19 21:22:31 +00:00
|
|
|
u32 db_debug3;
|
2009-09-08 00:10:24 +00:00
|
|
|
u32 num_gs_verts_per_thread;
|
|
|
|
u32 vgt_gs_per_es;
|
|
|
|
u32 gs_prim_buffer_depth = 0;
|
|
|
|
u32 sq_ms_fifo_sizes;
|
|
|
|
u32 sq_config;
|
|
|
|
u32 sq_thread_resource_mgmt;
|
|
|
|
u32 hdp_host_path_cntl;
|
|
|
|
u32 sq_dyn_gpr_size_simd_ab_0;
|
|
|
|
u32 backend_map;
|
|
|
|
u32 gb_tiling_config = 0;
|
|
|
|
u32 cc_rb_backend_disable = 0;
|
|
|
|
u32 cc_gc_shader_pipe_config = 0;
|
|
|
|
u32 mc_arb_ramcfg;
|
|
|
|
u32 db_debug4;
|
2009-06-05 12:42:42 +00:00
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
/* setup chip specs */
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_RV770:
|
|
|
|
rdev->config.rv770.max_pipes = 4;
|
|
|
|
rdev->config.rv770.max_tile_pipes = 8;
|
|
|
|
rdev->config.rv770.max_simds = 10;
|
|
|
|
rdev->config.rv770.max_backends = 4;
|
|
|
|
rdev->config.rv770.max_gprs = 256;
|
|
|
|
rdev->config.rv770.max_threads = 248;
|
|
|
|
rdev->config.rv770.max_stack_entries = 512;
|
|
|
|
rdev->config.rv770.max_hw_contexts = 8;
|
|
|
|
rdev->config.rv770.max_gs_threads = 16 * 2;
|
|
|
|
rdev->config.rv770.sx_max_export_size = 128;
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size = 16;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size = 112;
|
|
|
|
rdev->config.rv770.sq_num_cf_insts = 2;
|
|
|
|
|
|
|
|
rdev->config.rv770.sx_num_of_sets = 7;
|
|
|
|
rdev->config.rv770.sc_prim_fifo_size = 0xF9;
|
|
|
|
rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
|
|
|
|
break;
|
|
|
|
case CHIP_RV730:
|
|
|
|
rdev->config.rv770.max_pipes = 2;
|
|
|
|
rdev->config.rv770.max_tile_pipes = 4;
|
|
|
|
rdev->config.rv770.max_simds = 8;
|
|
|
|
rdev->config.rv770.max_backends = 2;
|
|
|
|
rdev->config.rv770.max_gprs = 128;
|
|
|
|
rdev->config.rv770.max_threads = 248;
|
|
|
|
rdev->config.rv770.max_stack_entries = 256;
|
|
|
|
rdev->config.rv770.max_hw_contexts = 8;
|
|
|
|
rdev->config.rv770.max_gs_threads = 16 * 2;
|
|
|
|
rdev->config.rv770.sx_max_export_size = 256;
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size = 32;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size = 224;
|
|
|
|
rdev->config.rv770.sq_num_cf_insts = 2;
|
|
|
|
|
|
|
|
rdev->config.rv770.sx_num_of_sets = 7;
|
|
|
|
rdev->config.rv770.sc_prim_fifo_size = 0xf9;
|
|
|
|
rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
|
|
|
|
if (rdev->config.rv770.sx_max_export_pos_size > 16) {
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size -= 16;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size += 16;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case CHIP_RV710:
|
|
|
|
rdev->config.rv770.max_pipes = 2;
|
|
|
|
rdev->config.rv770.max_tile_pipes = 2;
|
|
|
|
rdev->config.rv770.max_simds = 2;
|
|
|
|
rdev->config.rv770.max_backends = 1;
|
|
|
|
rdev->config.rv770.max_gprs = 256;
|
|
|
|
rdev->config.rv770.max_threads = 192;
|
|
|
|
rdev->config.rv770.max_stack_entries = 256;
|
|
|
|
rdev->config.rv770.max_hw_contexts = 4;
|
|
|
|
rdev->config.rv770.max_gs_threads = 8 * 2;
|
|
|
|
rdev->config.rv770.sx_max_export_size = 128;
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size = 16;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size = 112;
|
|
|
|
rdev->config.rv770.sq_num_cf_insts = 1;
|
|
|
|
|
|
|
|
rdev->config.rv770.sx_num_of_sets = 7;
|
|
|
|
rdev->config.rv770.sc_prim_fifo_size = 0x40;
|
|
|
|
rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
|
|
|
|
break;
|
|
|
|
case CHIP_RV740:
|
|
|
|
rdev->config.rv770.max_pipes = 4;
|
|
|
|
rdev->config.rv770.max_tile_pipes = 4;
|
|
|
|
rdev->config.rv770.max_simds = 8;
|
|
|
|
rdev->config.rv770.max_backends = 4;
|
|
|
|
rdev->config.rv770.max_gprs = 256;
|
|
|
|
rdev->config.rv770.max_threads = 248;
|
|
|
|
rdev->config.rv770.max_stack_entries = 512;
|
|
|
|
rdev->config.rv770.max_hw_contexts = 8;
|
|
|
|
rdev->config.rv770.max_gs_threads = 16 * 2;
|
|
|
|
rdev->config.rv770.sx_max_export_size = 256;
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size = 32;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size = 224;
|
|
|
|
rdev->config.rv770.sq_num_cf_insts = 2;
|
|
|
|
|
|
|
|
rdev->config.rv770.sx_num_of_sets = 7;
|
|
|
|
rdev->config.rv770.sc_prim_fifo_size = 0x100;
|
|
|
|
rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
|
|
|
|
|
|
|
|
if (rdev->config.rv770.sx_max_export_pos_size > 16) {
|
|
|
|
rdev->config.rv770.sx_max_export_pos_size -= 16;
|
|
|
|
rdev->config.rv770.sx_max_export_smx_size += 16;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize HDP */
|
|
|
|
j = 0;
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
WREG32((0x2c14 + j), 0x00000000);
|
|
|
|
WREG32((0x2c18 + j), 0x00000000);
|
|
|
|
WREG32((0x2c1c + j), 0x00000000);
|
|
|
|
WREG32((0x2c20 + j), 0x00000000);
|
|
|
|
WREG32((0x2c24 + j), 0x00000000);
|
|
|
|
j += 0x18;
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
|
|
|
|
|
|
|
/* setup tiling, simd, pipe config */
|
|
|
|
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
|
|
|
|
|
|
|
|
switch (rdev->config.rv770.max_tile_pipes) {
|
|
|
|
case 1:
|
2010-02-19 21:22:31 +00:00
|
|
|
default:
|
2009-09-08 00:10:24 +00:00
|
|
|
gb_tiling_config |= PIPE_TILING(0);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
gb_tiling_config |= PIPE_TILING(1);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
gb_tiling_config |= PIPE_TILING(2);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
gb_tiling_config |= PIPE_TILING(3);
|
|
|
|
break;
|
|
|
|
}
|
2010-02-19 21:22:31 +00:00
|
|
|
rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
if (rdev->family == CHIP_RV770)
|
|
|
|
gb_tiling_config |= BANK_TILING(1);
|
|
|
|
else
|
2009-11-03 15:04:01 +00:00
|
|
|
gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
|
2010-02-10 22:30:05 +00:00
|
|
|
rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
gb_tiling_config |= GROUP_SIZE(0);
|
2010-02-10 22:30:05 +00:00
|
|
|
rdev->config.rv770.tiling_group_size = 256;
|
2009-09-08 00:10:24 +00:00
|
|
|
|
2009-11-03 15:04:01 +00:00
|
|
|
if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
|
2009-09-08 00:10:24 +00:00
|
|
|
gb_tiling_config |= ROW_TILING(3);
|
|
|
|
gb_tiling_config |= SAMPLE_SPLIT(3);
|
|
|
|
} else {
|
|
|
|
gb_tiling_config |=
|
|
|
|
ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
|
|
|
|
gb_tiling_config |=
|
|
|
|
SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
|
|
|
|
}
|
|
|
|
|
|
|
|
gb_tiling_config |= BANK_SWAPS(1);
|
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
|
|
|
|
cc_rb_backend_disable |=
|
|
|
|
BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
|
2009-09-08 00:10:24 +00:00
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
|
|
|
|
cc_gc_shader_pipe_config |=
|
2009-09-08 00:10:24 +00:00
|
|
|
INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
|
|
|
|
cc_gc_shader_pipe_config |=
|
|
|
|
INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
|
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
if (rdev->family == CHIP_RV740)
|
|
|
|
backend_map = 0x28;
|
|
|
|
else
|
|
|
|
backend_map = r700_get_tile_pipe_to_backend_map(rdev,
|
|
|
|
rdev->config.rv770.max_tile_pipes,
|
|
|
|
(R7XX_MAX_BACKENDS -
|
|
|
|
r600_count_pipe_bits((cc_rb_backend_disable &
|
|
|
|
R7XX_MAX_BACKENDS_MASK) >> 16)),
|
|
|
|
(cc_rb_backend_disable >> 16));
|
|
|
|
gb_tiling_config |= BACKEND_MAP(backend_map);
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(GB_TILING_CONFIG, gb_tiling_config);
|
|
|
|
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
|
|
|
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
|
|
|
|
|
|
|
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
|
|
|
WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
2010-03-05 19:50:37 +00:00
|
|
|
WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
2010-02-19 21:22:31 +00:00
|
|
|
WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(CGTS_SYS_TCC_DISABLE, 0);
|
|
|
|
WREG32(CGTS_TCC_DISABLE, 0);
|
2010-03-05 19:50:37 +00:00
|
|
|
WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
|
|
|
|
WREG32(CGTS_USER_TCC_DISABLE, 0);
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
num_qd_pipes =
|
2010-02-19 21:22:31 +00:00
|
|
|
R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
|
2009-09-08 00:10:24 +00:00
|
|
|
WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
|
|
|
|
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
|
|
|
|
|
|
|
|
/* set HW defaults for 3D engine */
|
|
|
|
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
|
2009-11-03 15:04:01 +00:00
|
|
|
ROQ_IB2_START(0x2b)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
|
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
ta_aux_cntl = RREG32(TA_CNTL_AUX);
|
|
|
|
WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
sx_debug_1 = RREG32(SX_DEBUG_1);
|
|
|
|
sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
|
|
|
|
WREG32(SX_DEBUG_1, sx_debug_1);
|
|
|
|
|
|
|
|
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
|
|
|
|
smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
|
|
|
|
smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
|
|
|
|
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
|
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
if (rdev->family != CHIP_RV740)
|
|
|
|
WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
|
|
|
|
GS_FLUSH_CTL(4) |
|
|
|
|
ACK_FLUSH_CTL(3) |
|
|
|
|
SYNC_FLUSH_CTL));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
2010-02-19 21:22:31 +00:00
|
|
|
db_debug3 = RREG32(DB_DEBUG3);
|
|
|
|
db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_RV770:
|
|
|
|
case CHIP_RV740:
|
|
|
|
db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
|
|
|
|
break;
|
|
|
|
case CHIP_RV710:
|
|
|
|
case CHIP_RV730:
|
|
|
|
default:
|
|
|
|
db_debug3 |= DB_CLK_OFF_DELAY(2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
WREG32(DB_DEBUG3, db_debug3);
|
|
|
|
|
|
|
|
if (rdev->family != CHIP_RV770) {
|
2009-09-08 00:10:24 +00:00
|
|
|
db_debug4 = RREG32(DB_DEBUG4);
|
|
|
|
db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
|
|
|
|
WREG32(DB_DEBUG4, db_debug4);
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
|
2009-11-03 15:04:01 +00:00
|
|
|
POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
|
|
|
|
SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
|
2009-11-03 15:04:01 +00:00
|
|
|
SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
|
|
|
|
SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
|
|
|
|
|
|
|
|
WREG32(VGT_NUM_INSTANCES, 1);
|
|
|
|
|
|
|
|
WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
|
|
|
|
|
|
|
|
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
|
|
|
|
|
|
|
|
WREG32(CP_PERFMON_CNTL, 0);
|
|
|
|
|
|
|
|
sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
|
|
|
|
DONE_FIFO_HIWATER(0xe0) |
|
|
|
|
ALU_UPDATE_FIFO_HIWATER(0x8));
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_RV770:
|
|
|
|
case CHIP_RV730:
|
|
|
|
case CHIP_RV710:
|
2010-02-19 21:22:31 +00:00
|
|
|
sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
|
|
|
|
break;
|
2009-09-08 00:10:24 +00:00
|
|
|
case CHIP_RV740:
|
|
|
|
default:
|
|
|
|
sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
|
|
|
|
|
|
|
|
/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
|
|
|
|
* should be adjusted as needed by the 2D/3D drivers. This just sets default values
|
|
|
|
*/
|
|
|
|
sq_config = RREG32(SQ_CONFIG);
|
|
|
|
sq_config &= ~(PS_PRIO(3) |
|
|
|
|
VS_PRIO(3) |
|
|
|
|
GS_PRIO(3) |
|
|
|
|
ES_PRIO(3));
|
|
|
|
sq_config |= (DX9_CONSTS |
|
|
|
|
VC_ENABLE |
|
|
|
|
EXPORT_SRC_C |
|
|
|
|
PS_PRIO(0) |
|
|
|
|
VS_PRIO(1) |
|
|
|
|
GS_PRIO(2) |
|
|
|
|
ES_PRIO(3));
|
|
|
|
if (rdev->family == CHIP_RV710)
|
|
|
|
/* no vertex cache */
|
|
|
|
sq_config &= ~VC_ENABLE;
|
|
|
|
|
|
|
|
WREG32(SQ_CONFIG, sq_config);
|
|
|
|
|
|
|
|
WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
|
2009-09-21 04:06:30 +00:00
|
|
|
NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
|
|
|
|
NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
|
2009-09-21 04:06:30 +00:00
|
|
|
NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
|
|
|
|
NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
|
|
|
|
NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
|
|
|
|
if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
|
|
|
|
sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
|
|
|
|
else
|
|
|
|
sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
|
|
|
|
WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
|
|
|
|
|
|
|
|
WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
|
|
|
|
NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
|
|
|
|
|
|
|
|
WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
|
|
|
|
NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
|
|
|
|
|
|
|
|
sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
|
|
|
|
SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
|
|
|
|
SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
|
|
|
|
SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
|
|
|
|
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
|
|
|
|
|
|
|
|
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
|
2009-09-21 04:06:30 +00:00
|
|
|
FORCE_EOV_MAX_REZ_CNT(255)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
if (rdev->family == CHIP_RV710)
|
|
|
|
WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
|
2009-09-21 04:06:30 +00:00
|
|
|
AUTO_INVLD_EN(ES_AND_GS_AUTO)));
|
2009-09-08 00:10:24 +00:00
|
|
|
else
|
|
|
|
WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
|
2009-09-21 04:06:30 +00:00
|
|
|
AUTO_INVLD_EN(ES_AND_GS_AUTO)));
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_RV770:
|
|
|
|
case CHIP_RV730:
|
|
|
|
case CHIP_RV740:
|
|
|
|
gs_prim_buffer_depth = 384;
|
|
|
|
break;
|
|
|
|
case CHIP_RV710:
|
|
|
|
gs_prim_buffer_depth = 128;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
|
|
|
|
vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
|
|
|
|
/* Max value for this is 256 */
|
|
|
|
if (vgt_gs_per_es > 256)
|
|
|
|
vgt_gs_per_es = 256;
|
|
|
|
|
|
|
|
WREG32(VGT_ES_PER_GS, 128);
|
|
|
|
WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
|
|
|
|
WREG32(VGT_GS_PER_VS, 2);
|
|
|
|
|
|
|
|
/* more default values. 2D/3D driver should adjust as needed */
|
|
|
|
WREG32(VGT_GS_VERTEX_REUSE, 16);
|
|
|
|
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
|
|
|
|
WREG32(VGT_STRMOUT_EN, 0);
|
|
|
|
WREG32(SX_MISC, 0);
|
|
|
|
WREG32(PA_SC_MODE_CNTL, 0);
|
|
|
|
WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
|
|
|
|
WREG32(PA_SC_AA_CONFIG, 0);
|
|
|
|
WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
|
|
|
|
WREG32(PA_SC_LINE_STIPPLE, 0);
|
|
|
|
WREG32(SPI_INPUT_Z, 0);
|
|
|
|
WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
|
|
|
|
WREG32(CB_COLOR7_FRAG, 0);
|
|
|
|
|
|
|
|
/* clear render buffer base addresses */
|
|
|
|
WREG32(CB_COLOR0_BASE, 0);
|
|
|
|
WREG32(CB_COLOR1_BASE, 0);
|
|
|
|
WREG32(CB_COLOR2_BASE, 0);
|
|
|
|
WREG32(CB_COLOR3_BASE, 0);
|
|
|
|
WREG32(CB_COLOR4_BASE, 0);
|
|
|
|
WREG32(CB_COLOR5_BASE, 0);
|
|
|
|
WREG32(CB_COLOR6_BASE, 0);
|
|
|
|
WREG32(CB_COLOR7_BASE, 0);
|
|
|
|
|
|
|
|
WREG32(TCP_CNTL, 0);
|
|
|
|
|
|
|
|
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
|
|
|
|
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
|
|
|
|
|
|
|
|
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
|
|
|
|
|
|
|
|
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
|
|
|
|
NUM_CLIP_SEQ(3)));
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
int rv770_mc_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
u32 tmp;
|
2009-10-19 21:23:33 +00:00
|
|
|
int chansize, numchan;
|
2009-09-08 00:10:24 +00:00
|
|
|
|
|
|
|
/* Get VRAM informations */
|
|
|
|
rdev->mc.vram_is_ddr = true;
|
2009-10-19 21:23:33 +00:00
|
|
|
tmp = RREG32(MC_ARB_RAMCFG);
|
|
|
|
if (tmp & CHANSIZE_OVERRIDE) {
|
|
|
|
chansize = 16;
|
|
|
|
} else if (tmp & CHANSIZE_MASK) {
|
|
|
|
chansize = 64;
|
|
|
|
} else {
|
|
|
|
chansize = 32;
|
|
|
|
}
|
|
|
|
tmp = RREG32(MC_SHARED_CHMAP);
|
|
|
|
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
numchan = 1;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
numchan = 2;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
numchan = 4;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
numchan = 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
rdev->mc.vram_width = numchan * chansize;
|
2009-06-05 12:42:42 +00:00
|
|
|
/* Could aper size report 0 ? */
|
|
|
|
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
|
|
|
|
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
|
2009-09-08 00:10:24 +00:00
|
|
|
/* Setup GPU memory space */
|
|
|
|
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
|
|
|
|
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
|
2010-02-19 14:33:54 +00:00
|
|
|
rdev->mc.visible_vram_size = rdev->mc.aper_size;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
r600_vram_gtt_location(rdev, &rdev->mc);
|
2010-03-17 00:54:38 +00:00
|
|
|
radeon_update_bandwidth_info(rdev);
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
|
2009-09-18 05:19:37 +00:00
|
|
|
static int rv770_startup(struct radeon_device *rdev)
|
2009-09-08 00:10:24 +00:00
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
2009-12-10 00:31:44 +00:00
|
|
|
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
|
|
|
|
r = r600_init_microcode(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to load firmware!\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-01 16:02:13 +00:00
|
|
|
rv770_mc_program(rdev);
|
2009-10-06 17:04:30 +00:00
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
rv770_agp_enable(rdev);
|
|
|
|
} else {
|
|
|
|
r = rv770_pcie_gart_enable(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
rv770_gpu_init(rdev);
|
2010-02-04 16:27:27 +00:00
|
|
|
r = r600_blit_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
r600_blit_fini(rdev);
|
|
|
|
rdev->asic->copy = NULL;
|
|
|
|
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
|
|
|
}
|
2010-01-22 14:19:00 +00:00
|
|
|
/* pin copy shader into vram */
|
|
|
|
if (rdev->r600_blit.shader_obj) {
|
|
|
|
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
|
|
if (unlikely(r != 0))
|
|
|
|
return r;
|
|
|
|
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
|
|
|
|
&rdev->r600_blit.shader_gpu_addr);
|
|
|
|
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
2009-12-15 22:15:07 +00:00
|
|
|
if (r) {
|
2010-01-22 14:19:00 +00:00
|
|
|
DRM_ERROR("failed to pin blit object %d\n", r);
|
2009-12-15 22:15:07 +00:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
2009-12-01 18:43:46 +00:00
|
|
|
/* Enable IRQ */
|
|
|
|
r = r600_irq_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
r600_irq_set(rdev);
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
r = radeon_ring_init(rdev, rdev->cp.ring_size);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = rv770_cp_load_microcode(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = r600_cp_resume(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
2009-10-01 16:02:12 +00:00
|
|
|
/* write back buffer are not vital so don't worry about failure */
|
|
|
|
r600_wb_enable(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-09-18 05:19:37 +00:00
|
|
|
int rv770_resume(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
2009-10-06 17:04:30 +00:00
|
|
|
/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
|
|
|
|
* posting will perform necessary task to bring back GPU into good
|
|
|
|
* shape.
|
|
|
|
*/
|
2009-09-18 05:19:37 +00:00
|
|
|
/* post card */
|
2009-10-01 16:02:15 +00:00
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
2009-09-18 05:19:37 +00:00
|
|
|
/* Initialize clocks */
|
|
|
|
r = radeon_clocks_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = rv770_startup(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("r600 startup failed on resume\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-10-01 16:02:11 +00:00
|
|
|
r = r600_ib_test(rdev);
|
2009-09-18 05:19:37 +00:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: failled testing IB (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
2010-03-06 13:03:36 +00:00
|
|
|
|
|
|
|
r = r600_audio_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "radeon: audio init failed\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-09-18 05:19:37 +00:00
|
|
|
return r;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
int rv770_suspend(struct radeon_device *rdev)
|
|
|
|
{
|
2009-11-20 13:29:23 +00:00
|
|
|
int r;
|
|
|
|
|
2010-03-06 13:03:36 +00:00
|
|
|
r600_audio_fini(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
/* FIXME: we should wait for ring to be empty */
|
|
|
|
r700_cp_stop(rdev);
|
2009-09-18 08:41:24 +00:00
|
|
|
rdev->cp.ready = false;
|
2010-01-15 13:44:37 +00:00
|
|
|
r600_irq_suspend(rdev);
|
2009-10-01 16:02:12 +00:00
|
|
|
r600_wb_disable(rdev);
|
2009-09-14 16:29:49 +00:00
|
|
|
rv770_pcie_gart_disable(rdev);
|
2009-09-18 08:41:24 +00:00
|
|
|
/* unpin shaders bo */
|
2010-01-13 09:29:27 +00:00
|
|
|
if (rdev->r600_blit.shader_obj) {
|
|
|
|
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
|
|
if (likely(r == 0)) {
|
|
|
|
radeon_bo_unpin(rdev->r600_blit.shader_obj);
|
|
|
|
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
|
|
|
}
|
2009-11-20 13:29:23 +00:00
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Plan is to move initialization in that function and use
|
|
|
|
* helper function so that radeon_device_init pretty much
|
|
|
|
* do nothing more than calling asic specific function. This
|
|
|
|
* should also allow to remove a bunch of callback function
|
|
|
|
* like vram_info.
|
|
|
|
*/
|
|
|
|
int rv770_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = radeon_dummy_page_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* This don't do much */
|
|
|
|
r = radeon_gem_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* Read BIOS */
|
|
|
|
if (!radeon_get_bios(rdev)) {
|
|
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
/* Must be an ATOMBIOS */
|
2009-10-01 16:02:15 +00:00
|
|
|
if (!rdev->is_atom_bios) {
|
|
|
|
dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
|
2009-09-08 00:10:24 +00:00
|
|
|
return -EINVAL;
|
2009-10-01 16:02:15 +00:00
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
r = radeon_atombios_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* Post card if necessary */
|
2009-12-01 04:06:31 +00:00
|
|
|
if (!r600_card_posted(rdev)) {
|
|
|
|
if (!rdev->bios) {
|
|
|
|
dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
}
|
|
|
|
/* Initialize scratch registers */
|
|
|
|
r600_scratch_init(rdev);
|
|
|
|
/* Initialize surface registers */
|
|
|
|
radeon_surface_init(rdev);
|
2009-11-02 23:53:02 +00:00
|
|
|
/* Initialize clocks */
|
2009-09-17 07:42:28 +00:00
|
|
|
radeon_get_clock_info(rdev->ddev);
|
2009-09-08 00:10:24 +00:00
|
|
|
r = radeon_clocks_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* Fence driver */
|
|
|
|
r = radeon_fence_driver_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
/* initialize AGP */
|
2010-01-13 14:16:38 +00:00
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
r = radeon_agp_init(rdev);
|
|
|
|
if (r)
|
|
|
|
radeon_agp_disable(rdev);
|
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
r = rv770_mc_init(rdev);
|
2009-10-06 17:04:29 +00:00
|
|
|
if (r)
|
2009-09-08 00:10:24 +00:00
|
|
|
return r;
|
|
|
|
/* Memory manager */
|
2009-11-20 13:29:23 +00:00
|
|
|
r = radeon_bo_init(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
if (r)
|
|
|
|
return r;
|
2009-12-01 18:43:46 +00:00
|
|
|
|
|
|
|
r = radeon_irq_kms_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
rdev->cp.ring_obj = NULL;
|
|
|
|
r600_ring_init(rdev, 1024 * 1024);
|
|
|
|
|
2009-12-01 18:43:46 +00:00
|
|
|
rdev->ih.ring_obj = NULL;
|
|
|
|
r600_ih_ring_init(rdev, 64 * 1024);
|
|
|
|
|
2009-09-14 16:29:49 +00:00
|
|
|
r = r600_pcie_gart_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2009-12-10 00:31:44 +00:00
|
|
|
rdev->accel_working = true;
|
2009-09-18 05:19:37 +00:00
|
|
|
r = rv770_startup(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
if (r) {
|
2010-02-02 10:51:45 +00:00
|
|
|
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
2010-03-24 17:36:43 +00:00
|
|
|
r700_cp_fini(rdev);
|
2009-10-01 16:02:14 +00:00
|
|
|
r600_wb_fini(rdev);
|
2010-02-02 10:51:45 +00:00
|
|
|
r600_irq_fini(rdev);
|
|
|
|
radeon_irq_kms_fini(rdev);
|
2009-10-01 16:02:14 +00:00
|
|
|
rv770_pcie_gart_fini(rdev);
|
2009-09-16 13:24:21 +00:00
|
|
|
rdev->accel_working = false;
|
2009-09-08 00:10:24 +00:00
|
|
|
}
|
2009-09-16 13:24:21 +00:00
|
|
|
if (rdev->accel_working) {
|
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
|
|
if (r) {
|
2010-01-17 20:21:56 +00:00
|
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
2009-09-16 13:24:21 +00:00
|
|
|
rdev->accel_working = false;
|
2010-01-17 20:21:56 +00:00
|
|
|
} else {
|
|
|
|
r = r600_ib_test(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "IB test failed (%d).\n", r);
|
|
|
|
rdev->accel_working = false;
|
|
|
|
}
|
2009-09-16 13:24:21 +00:00
|
|
|
}
|
2009-09-08 00:10:24 +00:00
|
|
|
}
|
2010-03-06 13:03:36 +00:00
|
|
|
|
|
|
|
r = r600_audio_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "radeon: audio init failed\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void rv770_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
r600_blit_fini(rdev);
|
2010-03-24 17:36:43 +00:00
|
|
|
r700_cp_fini(rdev);
|
2010-02-02 10:51:45 +00:00
|
|
|
r600_wb_fini(rdev);
|
2009-12-01 18:43:46 +00:00
|
|
|
r600_irq_fini(rdev);
|
|
|
|
radeon_irq_kms_fini(rdev);
|
2009-09-14 16:29:49 +00:00
|
|
|
rv770_pcie_gart_fini(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
radeon_gem_fini(rdev);
|
|
|
|
radeon_fence_driver_fini(rdev);
|
|
|
|
radeon_clocks_fini(rdev);
|
2010-01-07 15:08:32 +00:00
|
|
|
radeon_agp_fini(rdev);
|
2009-11-20 13:29:23 +00:00
|
|
|
radeon_bo_fini(rdev);
|
2009-10-01 16:02:15 +00:00
|
|
|
radeon_atombios_fini(rdev);
|
2009-09-08 00:10:24 +00:00
|
|
|
kfree(rdev->bios);
|
|
|
|
rdev->bios = NULL;
|
|
|
|
radeon_dummy_page_fini(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|