297 lines
7.4 KiB
C
297 lines
7.4 KiB
C
![]() |
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - CPU frequency scaling support for EXYNOS series
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <linux/cpufreq.h>
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#include <linux/suspend.h>
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#include <linux/reboot.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-mem.h>
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#include <mach/cpufreq.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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static struct exynos_dvfs_info *exynos_info;
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static struct regulator *arm_regulator;
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static struct cpufreq_freqs freqs;
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static unsigned int locking_frequency;
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static bool frequency_locked;
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static DEFINE_MUTEX(cpufreq_lock);
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int exynos_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy,
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exynos_info->freq_table);
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}
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unsigned int exynos_getspeed(unsigned int cpu)
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{
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return clk_get_rate(exynos_info->cpu_clk) / 1000;
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}
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static int exynos_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int index, old_index;
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unsigned int arm_volt, safe_arm_volt = 0;
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int ret = 0;
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struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
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unsigned int *volt_table = exynos_info->volt_table;
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unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
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mutex_lock(&cpufreq_lock);
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freqs.old = policy->cur;
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if (frequency_locked && target_freq != locking_frequency) {
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ret = -EAGAIN;
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goto out;
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}
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if (cpufreq_frequency_table_target(policy, freq_table,
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freqs.old, relation, &old_index)) {
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ret = -EINVAL;
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goto out;
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}
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if (cpufreq_frequency_table_target(policy, freq_table,
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target_freq, relation, &index)) {
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ret = -EINVAL;
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goto out;
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}
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freqs.new = freq_table[index].frequency;
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freqs.cpu = policy->cpu;
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/*
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* ARM clock source will be changed APLL to MPLL temporary
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* To support this level, need to control regulator for
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* required voltage level
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*/
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if (exynos_info->need_apll_change != NULL) {
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if (exynos_info->need_apll_change(old_index, index) &&
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(freq_table[index].frequency < mpll_freq_khz) &&
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(freq_table[old_index].frequency < mpll_freq_khz))
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safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
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}
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arm_volt = volt_table[index];
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* When the new frequency is higher than current frequency */
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if ((freqs.new > freqs.old) && !safe_arm_volt) {
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/* Firstly, voltage up to increase frequency */
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regulator_set_voltage(arm_regulator, arm_volt,
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arm_volt);
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}
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if (safe_arm_volt)
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regulator_set_voltage(arm_regulator, safe_arm_volt,
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safe_arm_volt);
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if (freqs.new != freqs.old)
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exynos_info->set_freq(old_index, index);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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/* When the new frequency is lower than current frequency */
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if ((freqs.new < freqs.old) ||
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((freqs.new > freqs.old) && safe_arm_volt)) {
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/* down the voltage after frequency change */
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regulator_set_voltage(arm_regulator, arm_volt,
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arm_volt);
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}
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out:
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mutex_unlock(&cpufreq_lock);
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return ret;
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}
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#ifdef CONFIG_PM
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static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
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{
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return 0;
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}
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static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
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{
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return 0;
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}
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#endif
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/**
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* exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
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* context
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* @notifier
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* @pm_event
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* @v
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*
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* While frequency_locked == true, target() ignores every frequency but
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* locking_frequency. The locking_frequency value is the initial frequency,
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* which is set by the bootloader. In order to eliminate possible
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* inconsistency in clock values, we save and restore frequencies during
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* suspend and resume and block CPUFREQ activities. Note that the standard
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* suspend/resume cannot be used as they are too deep (syscore_ops) for
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* regulator actions.
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*/
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static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
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unsigned long pm_event, void *v)
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{
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struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
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static unsigned int saved_frequency;
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unsigned int temp;
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mutex_lock(&cpufreq_lock);
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switch (pm_event) {
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case PM_SUSPEND_PREPARE:
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if (frequency_locked)
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goto out;
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frequency_locked = true;
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if (locking_frequency) {
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saved_frequency = exynos_getspeed(0);
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mutex_unlock(&cpufreq_lock);
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exynos_target(policy, locking_frequency,
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CPUFREQ_RELATION_H);
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mutex_lock(&cpufreq_lock);
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}
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break;
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case PM_POST_SUSPEND:
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if (saved_frequency) {
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/*
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* While frequency_locked, only locking_frequency
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* is valid for target(). In order to use
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* saved_frequency while keeping frequency_locked,
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* we temporarly overwrite locking_frequency.
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*/
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temp = locking_frequency;
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locking_frequency = saved_frequency;
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mutex_unlock(&cpufreq_lock);
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exynos_target(policy, locking_frequency,
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CPUFREQ_RELATION_H);
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mutex_lock(&cpufreq_lock);
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locking_frequency = temp;
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}
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frequency_locked = false;
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break;
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}
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out:
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mutex_unlock(&cpufreq_lock);
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return NOTIFY_OK;
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}
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static struct notifier_block exynos_cpufreq_nb = {
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.notifier_call = exynos_cpufreq_pm_notifier,
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};
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static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
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cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
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/* set the transition latency value */
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policy->cpuinfo.transition_latency = 100000;
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/*
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* EXYNOS4 multi-core processors has 2 cores
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* that the frequency cannot be set independently.
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* Each cpu is bound to the same speed.
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* So the affected cpu is all of the cpus.
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*/
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if (num_online_cpus() == 1) {
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cpumask_copy(policy->related_cpus, cpu_possible_mask);
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cpumask_copy(policy->cpus, cpu_online_mask);
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} else {
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cpumask_setall(policy->cpus);
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}
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return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
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}
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static struct cpufreq_driver exynos_driver = {
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.flags = CPUFREQ_STICKY,
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.verify = exynos_verify_speed,
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.target = exynos_target,
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.get = exynos_getspeed,
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.init = exynos_cpufreq_cpu_init,
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.name = "exynos_cpufreq",
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#ifdef CONFIG_PM
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.suspend = exynos_cpufreq_suspend,
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.resume = exynos_cpufreq_resume,
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#endif
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};
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static int __init exynos_cpufreq_init(void)
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{
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int ret = -EINVAL;
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exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
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if (!exynos_info)
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return -ENOMEM;
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if (soc_is_exynos4210())
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ret = exynos4210_cpufreq_init(exynos_info);
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else
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pr_err("%s: CPU type not found\n", __func__);
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if (ret)
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goto err_vdd_arm;
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if (exynos_info->set_freq == NULL) {
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pr_err("%s: No set_freq function (ERR)\n", __func__);
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goto err_vdd_arm;
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}
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arm_regulator = regulator_get(NULL, "vdd_arm");
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if (IS_ERR(arm_regulator)) {
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pr_err("%s: failed to get resource vdd_arm\n", __func__);
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goto err_vdd_arm;
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}
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register_pm_notifier(&exynos_cpufreq_nb);
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if (cpufreq_register_driver(&exynos_driver)) {
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pr_err("%s: failed to register cpufreq driver\n", __func__);
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goto err_cpufreq;
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}
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return 0;
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err_cpufreq:
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unregister_pm_notifier(&exynos_cpufreq_nb);
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if (!IS_ERR(arm_regulator))
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regulator_put(arm_regulator);
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err_vdd_arm:
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kfree(exynos_info);
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pr_debug("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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late_initcall(exynos_cpufreq_init);
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