2009-04-23 20:15:04 +00:00
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/*
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*
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* arch/arm/mach-u300/include/mach/gpio.h
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*
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*
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* Copyright (C) 2007-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* GPIO block resgister definitions and inline macros for
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* U300 GPIO COH 901 335 or COH 901 571/3
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#ifndef __MACH_U300_GPIO_H
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#define __MACH_U300_GPIO_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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/* Switch type depending on platform/chip variant */
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#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
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#define U300_COH901335
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#endif
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#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
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#define U300_COH901571_3
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#endif
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/* Get base address for regs here */
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#include "u300-regs.h"
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/* IRQ numbers */
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#include "irqs.h"
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/*
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* This is the GPIO block definitions. GPIO (General Purpose I/O) can be
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* used for anything, and often is. The event/enable etc figures are for
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* the lowermost pin (pin 0 on each port), shift this left to match your
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* pin if you're gonna use these values.
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*/
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#ifdef U300_COH901335
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#define U300_GPIO_PORTX_SPACING (0x1C)
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/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
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#define U300_GPIO_PXPDIR (0x00)
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#define U300_GPIO_PXPDOR (0x00)
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/* Port X Pin Config Register 32bit (R/W) */
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#define U300_GPIO_PXPCR (0x04)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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/* Port X Interrupt Event Register 32bit (R/W) */
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#define U300_GPIO_PXIEV (0x08)
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#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
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/* Port X Interrupt Enable Register 32bit (R/W) */
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#define U300_GPIO_PXIEN (0x0C)
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#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
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/* Port X Interrupt Force Register 32bit (R/W) */
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#define U300_GPIO_PXIFR (0x10)
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#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
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/* Port X Interrupt Config Register 32bit (R/W) */
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#define U300_GPIO_PXICR (0x14)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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/* Port X Pull-up Enable Register 32bit (R/W) */
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#define U300_GPIO_PXPER (0x18)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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/* Control Register 32bit (R/W) */
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#define U300_GPIO_CR (0x54)
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#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
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/* three ports of 8 bits each = GPIO pins 0..23 */
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#define U300_GPIO_NUM_PORTS 3
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#define U300_GPIO_PINS_PER_PORT 8
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#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
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#endif
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#ifdef U300_COH901571_3
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/*
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* Control Register 32bit (R/W)
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* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
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* gives the number of GPIO pins.
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* bit 8-2 (mask 0x000001FC) contains the core version ID.
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*/
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#define U300_GPIO_CR (0x00)
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#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
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#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
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#define U300_GPIO_PORTX_SPACING (0x30)
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/* Port X Pin Data INPUT Register 32bit (R/W) */
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#define U300_GPIO_PXPDIR (0x04)
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/* Port X Pin Data OUTPUT Register 32bit (R/W) */
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#define U300_GPIO_PXPDOR (0x08)
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/* Port X Pin Config Register 32bit (R/W) */
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#define U300_GPIO_PXPCR (0x0C)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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/* Port X Pull-up Enable Register 32bit (R/W) */
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#define U300_GPIO_PXPER (0x10)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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/* Port X Interrupt Event Register 32bit (R/W) */
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#define U300_GPIO_PXIEV (0x14)
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#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
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/* Port X Interrupt Enable Register 32bit (R/W) */
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#define U300_GPIO_PXIEN (0x18)
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#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
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/* Port X Interrupt Force Register 32bit (R/W) */
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#define U300_GPIO_PXIFR (0x1C)
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#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
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/* Port X Interrupt Config Register 32bit (R/W) */
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#define U300_GPIO_PXICR (0x20)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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#ifdef CONFIG_MACH_U300_BS335
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/* seven ports of 8 bits each = GPIO pins 0..55 */
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#define U300_GPIO_NUM_PORTS 7
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#else
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/* five ports of 8 bits each = GPIO pins 0..39 */
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#define U300_GPIO_NUM_PORTS 5
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#endif
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#define U300_GPIO_PINS_PER_PORT 8
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#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
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#endif
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/*
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* Individual pin assignments for the B26/S26. Notice that the
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* actual usage of these pins depends on the PAD MUX settings, that
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* is why the same number can potentially appear several times.
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* In the reference design each pin is only used for one purpose.
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* These were determined by inspecting the B26/S26 schematic:
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* 2/1911-ROA 128 1603
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*/
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#ifdef CONFIG_MACH_U300_BS2X
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#define U300_GPIO_PIN_UART_RX 0
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#define U300_GPIO_PIN_UART_TX 1
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#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
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#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
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#define U300_GPIO_PIN_CAM_SLEEP 4
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#define U300_GPIO_PIN_CAM_REG_EN 5
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#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
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#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
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#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
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#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
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#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
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#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
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#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
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#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
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#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
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#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
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#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
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#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
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#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
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#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
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#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
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#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
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#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
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#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
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#endif
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/*
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* Individual pin assignments for the B330/S330 and B365/S365.
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* Notice that the actual usage of these pins depends on the
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* PAD MUX settings, that is why the same number can potentially
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* appear several times. In the reference design each pin is only
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* used for one purpose. These were determined by inspecting the
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* S365 schematic.
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*/
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#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
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defined(CONFIG_MACH_U300_BS335)
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#define U300_GPIO_PIN_UART_RX 0
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#define U300_GPIO_PIN_UART_TX 1
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#define U300_GPIO_PIN_UART_CTS 2
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#define U300_GPIO_PIN_UART_RTS 3
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#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
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#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
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#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
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#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
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#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
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#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
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#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
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#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
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#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
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#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
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#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
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#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
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#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
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#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
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#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
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#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
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#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
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#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
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#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
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#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
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#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
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#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
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#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
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#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
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#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
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#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
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#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
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#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
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#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
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#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
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#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
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#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
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#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
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#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
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#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
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#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
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#ifdef CONFIG_MACH_U300_BS335
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#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
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#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
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#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
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#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
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#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
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#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
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#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
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#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
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#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
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#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
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#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
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#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
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#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
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#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
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#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
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#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
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#endif
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#endif
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/* translates a pin number to a port number */
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#define PIN_TO_PORT(val) (val >> 3)
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/* These can be found in arch/arm/mach-u300/gpio.c */
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2009-09-28 11:36:18 +00:00
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extern int gpio_is_valid(int number);
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2009-04-23 20:15:04 +00:00
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extern int gpio_request(unsigned gpio, const char *label);
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extern void gpio_free(unsigned gpio);
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extern int gpio_direction_input(unsigned gpio);
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extern int gpio_direction_output(unsigned gpio, int value);
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extern int gpio_register_callback(unsigned gpio,
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int (*func)(void *arg),
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void *);
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extern int gpio_unregister_callback(unsigned gpio);
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extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
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extern void disable_irq_on_gpio_pin(unsigned gpio);
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extern void gpio_pullup(unsigned gpio, int value);
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extern int gpio_get_value(unsigned gpio);
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extern void gpio_set_value(unsigned gpio, int value);
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/* wrappers to sleep-enable the previous two functions */
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static inline unsigned gpio_to_irq(unsigned gpio)
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{
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return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
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}
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static inline unsigned irq_to_gpio(unsigned irq)
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{
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/*
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* FIXME: This is no 1-1 mapping at all, it points to the
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* whole block of 8 pins.
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*/
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return (irq - IRQ_U300_GPIO_PORT0) << 3;
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}
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#endif
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