2010-08-24 03:24:12 +00:00
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/*
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* Linux network driver for Brocade Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*/
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#ifndef __BFI_H__
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#define __BFI_H__
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#include "bfa_defs.h"
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#pragma pack(1)
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/**
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* BFI FW image type
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*/
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#define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */
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#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
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/**
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* Msg header common to all msgs
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*/
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struct bfi_mhdr {
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u8 msg_class; /*!< @ref enum bfi_mclass */
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u8 msg_id; /*!< msg opcode with in the class */
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union {
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struct {
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
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u8 qid;
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u8 fn_lpu; /*!< msg destination */
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2010-08-24 03:24:12 +00:00
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} h2i;
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u16 i2htok; /*!< token in msgs to host */
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} mtag;
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};
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
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#define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
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#define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
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#define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid)
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#define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \
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2011-07-22 08:07:41 +00:00
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(_mh).msg_class = (_mc); \
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2010-08-24 03:24:12 +00:00
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(_mh).msg_id = (_op); \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
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(_mh).mtag.h2i.fn_lpu = (_fn_lpu); \
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2010-08-24 03:24:12 +00:00
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} while (0)
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#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
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2011-07-22 08:07:41 +00:00
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(_mh).msg_class = (_mc); \
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2010-08-24 03:24:12 +00:00
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(_mh).msg_id = (_op); \
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(_mh).mtag.i2htok = (_i2htok); \
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} while (0)
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/*
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* Message opcodes: 0-127 to firmware, 128-255 to host
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*/
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#define BFI_I2H_OPCODE_BASE 128
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2011-07-22 08:07:41 +00:00
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#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
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2010-08-24 03:24:12 +00:00
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/**
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****************************************************************************
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*
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* Scatter Gather Element and Page definition
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*
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****************************************************************************
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*/
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/**
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* DMA addresses
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*/
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union bfi_addr_u {
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struct {
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u32 addr_lo;
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u32 addr_hi;
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} a32;
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};
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2011-12-22 13:29:45 +00:00
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/**
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* Generic DMA addr-len pair.
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*/
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struct bfi_alen {
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union bfi_addr_u al_addr; /* DMA addr of buffer */
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u32 al_len; /* length of buffer */
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};
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2010-08-24 03:24:12 +00:00
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/*
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* Large Message structure - 128 Bytes size Msgs
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*/
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#define BFI_LMSG_SZ 128
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#define BFI_LMSG_PL_WSZ \
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((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
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/**
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* Mailbox message structure
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*/
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#define BFI_MBMSG_SZ 7
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struct bfi_mbmsg {
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struct bfi_mhdr mh;
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u32 pl[BFI_MBMSG_SZ];
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};
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|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
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/**
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* Supported PCI function class codes (personality)
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*/
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enum bfi_pcifn_class {
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BFI_PCIFN_CLASS_FC = 0x0c04,
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BFI_PCIFN_CLASS_ETH = 0x0200,
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};
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2010-08-24 03:24:12 +00:00
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/**
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* Message Classes
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*/
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enum bfi_mclass {
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BFI_MC_IOC = 1, /*!< IO Controller (IOC) */
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BFI_MC_DIAG = 2, /*!< Diagnostic Msgs */
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BFI_MC_FLASH = 3, /*!< Flash message class */
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BFI_MC_CEE = 4, /*!< CEE */
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BFI_MC_FCPORT = 5, /*!< FC port */
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BFI_MC_IOCFC = 6, /*!< FC - IO Controller (IOC) */
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BFI_MC_LL = 7, /*!< Link Layer */
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BFI_MC_UF = 8, /*!< Unsolicited frame receive */
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BFI_MC_FCXP = 9, /*!< FC Transport */
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BFI_MC_LPS = 10, /*!< lport fc login services */
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BFI_MC_RPORT = 11, /*!< Remote port */
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BFI_MC_ITNIM = 12, /*!< I-T nexus (Initiator mode) */
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BFI_MC_IOIM_READ = 13, /*!< read IO (Initiator mode) */
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BFI_MC_IOIM_WRITE = 14, /*!< write IO (Initiator mode) */
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BFI_MC_IOIM_IO = 15, /*!< IO (Initiator mode) */
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BFI_MC_IOIM = 16, /*!< IO (Initiator mode) */
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BFI_MC_IOIM_IOCOM = 17, /*!< good IO completion */
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BFI_MC_TSKIM = 18, /*!< Initiator Task management */
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BFI_MC_SBOOT = 19, /*!< SAN boot services */
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BFI_MC_IPFC = 20, /*!< IP over FC Msgs */
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BFI_MC_PORT = 21, /*!< Physical port */
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BFI_MC_SFP = 22, /*!< SFP module */
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BFI_MC_MSGQ = 23, /*!< MSGQ */
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BFI_MC_ENET = 24, /*!< ENET commands/responses */
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2011-09-27 10:39:09 +00:00
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BFI_MC_PHY = 25, /*!< External PHY message class */
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BFI_MC_NBOOT = 26, /*!< Network Boot */
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BFI_MC_TIO_READ = 27, /*!< read IO (Target mode) */
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BFI_MC_TIO_WRITE = 28, /*!< write IO (Target mode) */
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BFI_MC_TIO_DATA_XFERED = 29, /*!< ds transferred (target mode) */
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BFI_MC_TIO_IO = 30, /*!< IO (Target mode) */
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BFI_MC_TIO = 31, /*!< IO (target mode) */
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BFI_MC_MFG = 32, /*!< MFG/ASIC block commands */
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BFI_MC_EDMA = 33, /*!< EDMA copy commands */
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BFI_MC_MAX = 34
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2010-08-24 03:24:12 +00:00
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};
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#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
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2011-08-08 16:21:35 +00:00
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#define BFI_FWBOOT_ENV_OS 0
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2010-08-24 03:24:12 +00:00
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/**
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*----------------------------------------------------------------------
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* IOC
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*----------------------------------------------------------------------
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*/
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|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
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/**
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* Different asic generations
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*/
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enum bfi_asic_gen {
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BFI_ASIC_GEN_CB = 1,
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BFI_ASIC_GEN_CT = 2,
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2011-09-27 10:39:07 +00:00
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BFI_ASIC_GEN_CT2 = 3,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
enum bfi_asic_mode {
|
|
|
|
BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
|
|
|
|
BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
|
|
|
|
BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
|
|
|
|
BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
|
|
|
|
};
|
|
|
|
|
2010-08-24 03:24:12 +00:00
|
|
|
enum bfi_ioc_h2i_msgs {
|
|
|
|
BFI_IOC_H2I_ENABLE_REQ = 1,
|
|
|
|
BFI_IOC_H2I_DISABLE_REQ = 2,
|
|
|
|
BFI_IOC_H2I_GETATTR_REQ = 3,
|
|
|
|
BFI_IOC_H2I_DBG_SYNC = 4,
|
|
|
|
BFI_IOC_H2I_DBG_DUMP = 5,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum bfi_ioc_i2h_msgs {
|
|
|
|
BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
|
2011-07-22 08:07:41 +00:00
|
|
|
BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
|
|
|
|
BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
|
2010-08-24 03:24:12 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* BFI_IOC_H2I_GETATTR_REQ message
|
|
|
|
*/
|
|
|
|
struct bfi_ioc_getattr_req {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
union bfi_addr_u attr_addr;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct bfi_ioc_attr {
|
|
|
|
u64 mfg_pwwn; /*!< Mfg port wwn */
|
|
|
|
u64 mfg_nwwn; /*!< Mfg node wwn */
|
|
|
|
mac_t mfg_mac; /*!< Mfg mac */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
u8 port_mode; /* enum bfi_port_mode */
|
|
|
|
u8 rsvd_a;
|
2010-08-24 03:24:12 +00:00
|
|
|
u64 pwwn;
|
|
|
|
u64 nwwn;
|
|
|
|
mac_t mac; /*!< PBC or Mfg mac */
|
|
|
|
u16 rsvd_b;
|
|
|
|
mac_t fcoe_mac;
|
|
|
|
u16 rsvd_c;
|
|
|
|
char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
|
|
|
|
u8 pcie_gen;
|
|
|
|
u8 pcie_lanes_orig;
|
|
|
|
u8 pcie_lanes;
|
|
|
|
u8 rx_bbcredit; /*!< receive buffer credits */
|
|
|
|
u32 adapter_prop; /*!< adapter properties */
|
|
|
|
u16 maxfrsize; /*!< max receive frame size */
|
|
|
|
char asic_rev;
|
|
|
|
u8 rsvd_d;
|
|
|
|
char fw_version[BFA_VERSION_LEN];
|
|
|
|
char optrom_version[BFA_VERSION_LEN];
|
|
|
|
struct bfa_mfg_vpd vpd;
|
|
|
|
u32 card_type; /*!< card type */
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* BFI_IOC_I2H_GETATTR_REPLY message
|
|
|
|
*/
|
|
|
|
struct bfi_ioc_getattr_reply {
|
|
|
|
struct bfi_mhdr mh; /*!< Common msg header */
|
|
|
|
u8 status; /*!< cfg reply status */
|
|
|
|
u8 rsvd[3];
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Firmware memory page offsets
|
|
|
|
*/
|
|
|
|
#define BFI_IOC_SMEM_PG0_CB (0x40)
|
|
|
|
#define BFI_IOC_SMEM_PG0_CT (0x180)
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Firmware statistic offset
|
|
|
|
*/
|
|
|
|
#define BFI_IOC_FWSTATS_OFF (0x6B40)
|
|
|
|
#define BFI_IOC_FWSTATS_SZ (4096)
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Firmware trace offset
|
|
|
|
*/
|
|
|
|
#define BFI_IOC_TRC_OFF (0x4b00)
|
|
|
|
#define BFI_IOC_TRC_ENTS 256
|
2011-12-22 13:30:19 +00:00
|
|
|
#define BFI_IOC_TRC_ENT_SZ 16
|
|
|
|
#define BFI_IOC_TRC_HDR_SZ 32
|
2010-08-24 03:24:12 +00:00
|
|
|
|
|
|
|
#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
|
|
|
|
#define BFI_IOC_MD5SUM_SZ 4
|
|
|
|
struct bfi_ioc_image_hdr {
|
|
|
|
u32 signature; /*!< constant signature */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
u8 asic_gen; /*!< asic generation */
|
|
|
|
u8 asic_mode;
|
|
|
|
u8 port0_mode; /*!< device mode for port 0 */
|
|
|
|
u8 port1_mode; /*!< device mode for port 1 */
|
2010-08-24 03:24:12 +00:00
|
|
|
u32 exec; /*!< exec vector */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
u32 bootenv; /*!< firmware boot env */
|
2010-08-24 03:24:12 +00:00
|
|
|
u32 rsvd_b[4];
|
|
|
|
u32 md5sum[BFI_IOC_MD5SUM_SZ];
|
|
|
|
};
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
#define BFI_FWBOOT_DEVMODE_OFF 4
|
|
|
|
#define BFI_FWBOOT_TYPE_OFF 8
|
|
|
|
#define BFI_FWBOOT_ENV_OFF 12
|
|
|
|
#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
|
|
|
|
(((u32)(__asic_gen)) << 24 | \
|
|
|
|
((u32)(__asic_mode)) << 16 | \
|
|
|
|
((u32)(__p0_mode)) << 8 | \
|
|
|
|
((u32)(__p1_mode)))
|
|
|
|
|
2011-07-22 08:07:47 +00:00
|
|
|
enum bfi_fwboot_type {
|
|
|
|
BFI_FWBOOT_TYPE_NORMAL = 0,
|
|
|
|
BFI_FWBOOT_TYPE_FLASH = 1,
|
|
|
|
BFI_FWBOOT_TYPE_MEMTEST = 2,
|
|
|
|
};
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
enum bfi_port_mode {
|
|
|
|
BFI_PORT_MODE_FC = 1,
|
|
|
|
BFI_PORT_MODE_ETH = 2,
|
|
|
|
};
|
|
|
|
|
2010-08-24 03:24:12 +00:00
|
|
|
struct bfi_ioc_hbeat {
|
|
|
|
struct bfi_mhdr mh; /*!< common msg header */
|
|
|
|
u32 hb_count; /*!< current heart beat count */
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* IOC hardware/firmware state
|
|
|
|
*/
|
|
|
|
enum bfi_ioc_state {
|
|
|
|
BFI_IOC_UNINIT = 0, /*!< not initialized */
|
|
|
|
BFI_IOC_INITING = 1, /*!< h/w is being initialized */
|
|
|
|
BFI_IOC_HWINIT = 2, /*!< h/w is initialized */
|
|
|
|
BFI_IOC_CFG = 3, /*!< IOC configuration in progress */
|
|
|
|
BFI_IOC_OP = 4, /*!< IOC is operational */
|
|
|
|
BFI_IOC_DISABLING = 5, /*!< IOC is being disabled */
|
|
|
|
BFI_IOC_DISABLED = 6, /*!< IOC is disabled */
|
|
|
|
BFI_IOC_CFG_DISABLED = 7, /*!< IOC is being disabled;transient */
|
|
|
|
BFI_IOC_FAIL = 8, /*!< IOC heart-beat failure */
|
|
|
|
BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */
|
|
|
|
};
|
|
|
|
|
|
|
|
#define BFI_IOC_ENDIAN_SIG 0x12345678
|
|
|
|
|
|
|
|
enum {
|
|
|
|
BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */
|
|
|
|
BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */
|
|
|
|
BFI_ADAPTER_TYPE_SH = 16, /*!< adapter type shift */
|
|
|
|
BFI_ADAPTER_NPORTS_MK = 0xff00, /*!< number of ports mask */
|
|
|
|
BFI_ADAPTER_NPORTS_SH = 8, /*!< number of ports shift */
|
|
|
|
BFI_ADAPTER_SPEED_MK = 0xff, /*!< adapter speed mask */
|
|
|
|
BFI_ADAPTER_SPEED_SH = 0, /*!< adapter speed shift */
|
|
|
|
BFI_ADAPTER_PROTO = 0x100000, /*!< prototype adapaters */
|
|
|
|
BFI_ADAPTER_TTV = 0x200000, /*!< TTV debug capable */
|
|
|
|
BFI_ADAPTER_UNSUPP = 0x400000, /*!< unknown adapter type */
|
|
|
|
};
|
|
|
|
|
|
|
|
#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
|
|
|
|
(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
|
|
|
|
BFI_ADAPTER_ ## __prop ## _SH)
|
|
|
|
#define BFI_ADAPTER_SETP(__prop, __val) \
|
|
|
|
((__val) << BFI_ADAPTER_ ## __prop ## _SH)
|
|
|
|
#define BFI_ADAPTER_IS_PROTO(__adap_type) \
|
|
|
|
((__adap_type) & BFI_ADAPTER_PROTO)
|
|
|
|
#define BFI_ADAPTER_IS_TTV(__adap_type) \
|
|
|
|
((__adap_type) & BFI_ADAPTER_TTV)
|
|
|
|
#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
|
|
|
|
((__adap_type) & BFI_ADAPTER_UNSUPP)
|
|
|
|
#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
|
|
|
|
((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
|
|
|
|
BFI_ADAPTER_UNSUPP))
|
|
|
|
|
|
|
|
/**
|
|
|
|
* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
|
|
|
|
*/
|
|
|
|
struct bfi_ioc_ctrl_req {
|
|
|
|
struct bfi_mhdr mh;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
u16 clscode;
|
|
|
|
u16 rsvd;
|
2010-08-24 03:24:12 +00:00
|
|
|
u32 tv_sec;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
|
|
|
|
*/
|
|
|
|
struct bfi_ioc_ctrl_reply {
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
struct bfi_mhdr mh; /*!< Common msg header */
|
2010-08-24 03:24:12 +00:00
|
|
|
u8 status; /*!< enable/disable status */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
u8 port_mode; /*!< enum bfa_mode */
|
|
|
|
u8 cap_bm; /*!< capability bit mask */
|
|
|
|
u8 rsvd;
|
2010-08-24 03:24:12 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
#define BFI_IOC_MSGSZ 8
|
|
|
|
/**
|
|
|
|
* H2I Messages
|
|
|
|
*/
|
|
|
|
union bfi_ioc_h2i_msg_u {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
struct bfi_ioc_ctrl_req enable_req;
|
|
|
|
struct bfi_ioc_ctrl_req disable_req;
|
|
|
|
struct bfi_ioc_getattr_req getattr_req;
|
|
|
|
u32 mboxmsg[BFI_IOC_MSGSZ];
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* I2H Messages
|
|
|
|
*/
|
|
|
|
union bfi_ioc_i2h_msg_u {
|
|
|
|
struct bfi_mhdr mh;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 16:21:39 +00:00
|
|
|
struct bfi_ioc_ctrl_reply fw_event;
|
2010-08-24 03:24:12 +00:00
|
|
|
u32 mboxmsg[BFI_IOC_MSGSZ];
|
|
|
|
};
|
|
|
|
|
2011-08-08 16:21:35 +00:00
|
|
|
/**
|
|
|
|
*----------------------------------------------------------------------
|
|
|
|
* MSGQ
|
|
|
|
*----------------------------------------------------------------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
enum bfi_msgq_h2i_msgs {
|
|
|
|
BFI_MSGQ_H2I_INIT_REQ = 1,
|
|
|
|
BFI_MSGQ_H2I_DOORBELL_PI = 2,
|
|
|
|
BFI_MSGQ_H2I_DOORBELL_CI = 3,
|
|
|
|
BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum bfi_msgq_i2h_msgs {
|
|
|
|
BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
|
|
|
|
BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
|
|
|
|
BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
|
|
|
|
BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Messages(commands/responsed/AENS will have the following header */
|
|
|
|
struct bfi_msgq_mhdr {
|
|
|
|
u8 msg_class;
|
|
|
|
u8 msg_id;
|
|
|
|
u16 msg_token;
|
|
|
|
u16 num_entries;
|
|
|
|
u8 enet_id;
|
|
|
|
u8 rsvd[1];
|
|
|
|
};
|
|
|
|
|
|
|
|
#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
|
|
|
|
(_mh).msg_class = (_mc); \
|
|
|
|
(_mh).msg_id = (_mid); \
|
|
|
|
(_mh).msg_token = (_tok); \
|
|
|
|
(_mh).enet_id = (_enet_id); \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Mailbox for messaging interface
|
|
|
|
*/
|
|
|
|
#define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
|
|
|
|
#define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
|
|
|
|
|
|
|
|
#define bfi_msgq_num_cmd_entries(_size) \
|
|
|
|
(((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
|
|
|
|
|
|
|
|
struct bfi_msgq {
|
|
|
|
union bfi_addr_u addr;
|
|
|
|
u16 q_depth; /* Total num of entries in the queue */
|
|
|
|
u8 rsvd[2];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
|
|
|
|
struct bfi_msgq_cfg_req {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
struct bfi_msgq cmdq;
|
|
|
|
struct bfi_msgq rspq;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* BFI_ENET_MSGQ_CFG_RSP */
|
|
|
|
struct bfi_msgq_cfg_rsp {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
u8 cmd_status;
|
|
|
|
u8 rsvd[3];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* BFI_MSGQ_H2I_DOORBELL */
|
|
|
|
struct bfi_msgq_h2i_db {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
union {
|
|
|
|
u16 cmdq_pi;
|
|
|
|
u16 rspq_ci;
|
|
|
|
} idx;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* BFI_MSGQ_I2H_DOORBELL */
|
|
|
|
struct bfi_msgq_i2h_db {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
union {
|
|
|
|
u16 rspq_pi;
|
|
|
|
u16 cmdq_ci;
|
|
|
|
} idx;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define BFI_CMD_COPY_SZ 28
|
|
|
|
|
|
|
|
/* BFI_MSGQ_H2I_CMD_COPY_RSP */
|
|
|
|
struct bfi_msgq_h2i_cmdq_copy_rsp {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
u8 data[BFI_CMD_COPY_SZ];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* BFI_MSGQ_I2H_CMD_COPY_REQ */
|
|
|
|
struct bfi_msgq_i2h_cmdq_copy_req {
|
|
|
|
struct bfi_mhdr mh;
|
|
|
|
u16 offset;
|
|
|
|
u16 len;
|
|
|
|
};
|
|
|
|
|
2011-12-22 13:29:45 +00:00
|
|
|
/*
|
|
|
|
* FLASH module specific
|
|
|
|
*/
|
|
|
|
enum bfi_flash_h2i_msgs {
|
|
|
|
BFI_FLASH_H2I_QUERY_REQ = 1,
|
|
|
|
BFI_FLASH_H2I_ERASE_REQ = 2,
|
|
|
|
BFI_FLASH_H2I_WRITE_REQ = 3,
|
|
|
|
BFI_FLASH_H2I_READ_REQ = 4,
|
|
|
|
BFI_FLASH_H2I_BOOT_VER_REQ = 5,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum bfi_flash_i2h_msgs {
|
|
|
|
BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
|
|
|
|
BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
|
|
|
|
BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
|
|
|
|
BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
|
|
|
|
BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
|
|
|
|
BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash query request
|
|
|
|
*/
|
|
|
|
struct bfi_flash_query_req {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
struct bfi_alen alen;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash write request
|
|
|
|
*/
|
|
|
|
struct bfi_flash_write_req {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
struct bfi_alen alen;
|
|
|
|
u32 type; /* partition type */
|
|
|
|
u8 instance; /* partition instance */
|
|
|
|
u8 last;
|
|
|
|
u8 rsv[2];
|
|
|
|
u32 offset;
|
|
|
|
u32 length;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash read request
|
|
|
|
*/
|
|
|
|
struct bfi_flash_read_req {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
u32 type; /* partition type */
|
|
|
|
u8 instance; /* partition instance */
|
|
|
|
u8 rsv[3];
|
|
|
|
u32 offset;
|
|
|
|
u32 length;
|
|
|
|
struct bfi_alen alen;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash query response
|
|
|
|
*/
|
|
|
|
struct bfi_flash_query_rsp {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
u32 status;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash read response
|
|
|
|
*/
|
|
|
|
struct bfi_flash_read_rsp {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
u32 type; /* partition type */
|
|
|
|
u8 instance; /* partition instance */
|
|
|
|
u8 rsv[3];
|
|
|
|
u32 status;
|
|
|
|
u32 length;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flash write response
|
|
|
|
*/
|
|
|
|
struct bfi_flash_write_rsp {
|
|
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
|
|
u32 type; /* partition type */
|
|
|
|
u8 instance; /* partition instance */
|
|
|
|
u8 rsv[3];
|
|
|
|
u32 status;
|
|
|
|
u32 length;
|
|
|
|
};
|
|
|
|
|
2010-08-24 03:24:12 +00:00
|
|
|
#pragma pack()
|
|
|
|
|
|
|
|
#endif /* __BFI_H__ */
|