2007-12-12 06:44:46 +00:00
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/*
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* Copyright 2007, Olof Johansson, PA Semi
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*
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* Based on arch/powerpc/sysdev/mpic_u3msi.c:
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*
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* Copyright 2006, Segher Boessenkool, IBM Corporation.
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* Copyright 2006-2007, Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/msi.h>
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#include <asm/mpic.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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2008-08-05 23:10:03 +00:00
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#include <asm/msi_bitmap.h>
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2007-12-12 06:44:46 +00:00
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#include "mpic.h"
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/* Allocate 16 interrupts per device, to give an alignment of 16,
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* since that's the size of the grouping w.r.t. affinity. If someone
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* needs more than 32 MSI's down the road we'll have to rethink this,
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* but it should be OK for now.
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*/
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#define ALLOC_CHUNK 16
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#define PASEMI_MSI_ADDR 0xfc080000
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/* A bit ugly, can we get this from the pci_dev somehow? */
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static struct mpic *msi_mpic;
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2010-09-28 14:46:51 +00:00
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static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
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2007-12-12 06:44:46 +00:00
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{
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2010-09-28 14:46:51 +00:00
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pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
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mask_msi_irq(data);
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2011-03-08 22:26:43 +00:00
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mpic_mask_irq(data);
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2007-12-12 06:44:46 +00:00
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}
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2010-09-28 14:46:51 +00:00
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static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
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2007-12-12 06:44:46 +00:00
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{
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2010-09-28 14:46:51 +00:00
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pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
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2011-03-08 22:26:43 +00:00
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mpic_unmask_irq(data);
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2010-09-28 14:46:51 +00:00
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unmask_msi_irq(data);
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2007-12-12 06:44:46 +00:00
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}
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static struct irq_chip mpic_pasemi_msi_chip = {
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2011-03-08 22:26:43 +00:00
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.irq_shutdown = mpic_pasemi_msi_mask_irq,
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.irq_mask = mpic_pasemi_msi_mask_irq,
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.irq_unmask = mpic_pasemi_msi_unmask_irq,
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.irq_eoi = mpic_end_irq,
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.irq_set_type = mpic_set_irq_type,
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.irq_set_affinity = mpic_set_affinity,
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.name = "PASEMI-MSI",
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2007-12-12 06:44:46 +00:00
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};
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static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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{
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if (type == PCI_CAP_ID_MSIX)
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pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
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return 0;
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}
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static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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set_irq_msi(entry->irq, NULL);
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2008-08-05 23:10:03 +00:00
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
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virq_to_hw(entry->irq), ALLOC_CHUNK);
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2007-12-12 06:44:46 +00:00
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irq_dispose_mapping(entry->irq);
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}
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return;
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}
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static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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unsigned int virq;
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struct msi_desc *entry;
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struct msi_msg msg;
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2008-08-05 23:10:03 +00:00
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int hwirq;
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2007-12-12 06:44:46 +00:00
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pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
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pdev, nvec, type);
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msg.address_hi = 0;
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msg.address_lo = PASEMI_MSI_ADDR;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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/* Allocate 16 interrupts for now, since that's the grouping for
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* affinity. This can be changed later if it turns out 32 is too
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* few MSIs for someone, but restrictions will apply to how the
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* sources can be changed independently.
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*/
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2008-08-05 23:10:03 +00:00
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hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
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ALLOC_CHUNK);
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if (hwirq < 0) {
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2007-12-12 06:44:46 +00:00
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pr_debug("pasemi_msi: failed allocating hwirq\n");
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return hwirq;
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}
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virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
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if (virq == NO_IRQ) {
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2008-08-05 23:10:03 +00:00
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pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
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hwirq);
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
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ALLOC_CHUNK);
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2007-12-12 06:44:46 +00:00
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return -ENOSPC;
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}
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/* Vector on MSI is really an offset, the hardware adds
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* it to the value written at the magic address. So set
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* it to 0 to remain sane.
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*/
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mpic_set_vector(virq, 0);
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set_irq_msi(virq, entry);
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set_irq_chip(virq, &mpic_pasemi_msi_chip);
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set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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2008-08-05 23:10:03 +00:00
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pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
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"addr 0x%x\n", virq, hwirq, msg.address_lo);
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2007-12-12 06:44:46 +00:00
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/* Likewise, the device writes [0...511] into the target
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* register to generate MSI [512...1023]
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*/
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msg.data = hwirq-0x200;
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write_msi_msg(virq, &msg);
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}
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return 0;
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}
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int mpic_pasemi_msi_init(struct mpic *mpic)
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{
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int rc;
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if (!mpic->irqhost->of_node ||
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!of_device_is_compatible(mpic->irqhost->of_node,
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"pasemi,pwrficient-openpic"))
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return -ENODEV;
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rc = mpic_msi_init_allocator(mpic);
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if (rc) {
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pr_debug("pasemi_msi: Error allocating bitmap!\n");
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return rc;
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}
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pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
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msi_mpic = mpic;
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WARN_ON(ppc_md.setup_msi_irqs);
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ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
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ppc_md.msi_check_device = pasemi_msi_check_device;
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return 0;
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}
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