2007-05-08 21:27:46 +00:00
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/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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2009-04-27 18:02:22 +00:00
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#include <linux/init.h>
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2007-05-08 21:27:46 +00:00
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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2008-09-07 18:15:31 +00:00
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#include <asm/hwcap.h>
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2007-05-08 21:27:46 +00:00
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define TTB_S (1 << 1)
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2008-11-06 13:23:09 +00:00
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_OC_WBWA (1 << 3)
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2007-05-08 21:27:46 +00:00
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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2009-05-30 13:00:15 +00:00
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#define TTB_NOS (1 << 5)
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#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
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#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
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#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
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#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
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2007-05-08 21:27:46 +00:00
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2009-05-30 13:00:15 +00:00
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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2010-09-04 09:47:48 +00:00
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#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
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#define PMD_FLAGS_UP PMD_SECT_WB
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2009-05-30 13:00:15 +00:00
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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2010-09-04 09:47:48 +00:00
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#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
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#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
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2008-11-06 13:23:09 +00:00
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2007-05-08 21:27:46 +00:00
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_proc_init)
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2007-05-08 21:27:46 +00:00
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ENTRY(cpu_v7_proc_fin)
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2010-01-19 16:01:33 +00:00
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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2010-07-26 11:22:12 +00:00
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_proc_fin)
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2007-05-08 21:27:46 +00:00
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_v7_reset)
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mov pc, r0
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_reset)
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2007-05-08 21:27:46 +00:00
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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2008-11-10 14:14:11 +00:00
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dsb @ WFI may enter a low-power mode
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2008-10-03 10:09:10 +00:00
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wfi
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2007-05-08 21:27:46 +00:00
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_do_idle)
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2007-05-08 21:27:46 +00:00
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ENTRY(cpu_v7_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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dcache_line_size r2, r3
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 1b
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dsb
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#endif
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_dcache_clean_area)
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2007-05-08 21:27:46 +00:00
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v7_switch_mm)
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2007-07-20 10:43:02 +00:00
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#ifdef CONFIG_MMU
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2007-05-08 21:27:46 +00:00
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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2010-09-04 09:47:48 +00:00
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ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
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ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
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2009-04-30 16:06:09 +00:00
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#ifdef CONFIG_ARM_ERRATA_430973
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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2011-02-28 17:15:16 +00:00
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#endif
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2011-06-09 09:10:27 +00:00
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#ifdef CONFIG_ARM_ERRATA_754322
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dsb
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#endif
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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2007-05-08 21:27:46 +00:00
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isb
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2011-02-28 17:15:16 +00:00
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#ifdef CONFIG_ARM_ERRATA_754322
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dsb
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#endif
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2007-05-08 21:27:46 +00:00
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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2007-07-20 10:43:02 +00:00
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#endif
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2007-05-08 21:27:46 +00:00
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_switch_mm)
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2007-05-08 21:27:46 +00:00
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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2010-11-16 00:16:01 +00:00
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* (hardware version is stored at +2048 bytes)
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2007-05-08 21:27:46 +00:00
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*/
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ENTRY(cpu_v7_set_pte_ext)
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2007-07-20 10:43:02 +00:00
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#ifdef CONFIG_MMU
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2010-11-16 00:16:01 +00:00
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str r1, [r0] @ linux version
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2007-05-08 21:27:46 +00:00
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bic r3, r1, #0x000003f0
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2008-09-15 16:23:10 +00:00
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bic r3, r3, #PTE_TYPE_MASK
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2007-05-08 21:27:46 +00:00
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 10:52:28 +00:00
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tst r1, #1 << 4
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2008-09-15 16:23:10 +00:00
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orrne r3, r3, #PTE_EXT_TEX(1)
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2010-11-16 08:40:36 +00:00
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
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orrne r3, r3, #PTE_EXT_APX
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2007-05-08 21:27:46 +00:00
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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2010-09-13 15:03:21 +00:00
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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2007-05-08 21:27:46 +00:00
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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2010-09-13 15:03:21 +00:00
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#endif
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2007-05-08 21:27:46 +00:00
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2010-11-16 00:23:31 +00:00
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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2007-05-08 21:27:46 +00:00
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2008-09-15 16:23:10 +00:00
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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2007-05-08 21:27:46 +00:00
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moveq r3, #0
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2011-01-13 23:43:01 +00:00
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ARM( str r3, [r0, #2048]! )
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THUMB( add r0, r0, #2048 )
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THUMB( str r3, [r0] )
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2007-05-08 21:27:46 +00:00
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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2007-07-20 10:43:02 +00:00
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#endif
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2007-05-08 21:27:46 +00:00
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mov pc, lr
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2008-08-28 10:22:32 +00:00
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ENDPROC(cpu_v7_set_pte_ext)
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2007-05-08 21:27:46 +00:00
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cpu_v7_name:
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.ascii "ARMv7 Processor"
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.align
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2011-02-06 15:48:39 +00:00
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/*
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* Memory region attributes with SCTLR.TRE=1
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*
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* n = TEX[0],C,B
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* TR = PRRR[2n+1:2n] - memory type
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* IR = NMRR[2n+1:2n] - inner cacheable property
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* OR = NMRR[2n+17:2n+16] - outer cacheable property
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*
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* n TR IR OR
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* UNCACHED 000 00
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* BUFFERABLE 001 10 00 00
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* WRITETHROUGH 010 10 10 10
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* WRITEBACK 011 10 11 11
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* reserved 110
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* WRITEALLOC 111 10 01 01
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* DEV_SHARED 100 01
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* DEV_NONSHARED 100 01
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* DEV_WC 001 10
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* DEV_CACHED 011 10
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*
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* Other attributes:
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*
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* DS0 = PRRR[16] = 0 - device shareable property
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* DS1 = PRRR[17] = 1 - device shareable property
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* NS0 = PRRR[18] = 0 - normal shareable property
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* NS1 = PRRR[19] = 1 - normal shareable property
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* NOS = PRRR[24+n] = 1 - not outer shareable
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*/
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.equ PRRR, 0xff0a81a8
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.equ NMRR, 0x40e040e0
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 8
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2011-04-02 09:08:55 +00:00
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#ifdef CONFIG_PM_SLEEP
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2011-02-06 15:48:39 +00:00
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r11, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 1 @ Context ID
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 0 @ TTB 0
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mrc p15, 0, r8, c2, c0, 1 @ TTB 1
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
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stmia r0, {r4 - r11}
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_v7_do_suspend)
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ENTRY(cpu_v7_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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ldmia r0, {r4 - r11}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 1 @ Context ID
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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mcr p15, 0, r7, c2, c0, 0 @ TTB 0
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mcr p15, 0, r8, c2, c0, 1 @ TTB 1
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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2011-03-31 01:57:33 +00:00
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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2011-02-06 15:48:39 +00:00
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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isb
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mov r0, r9 @ control register
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, cpu_resume_l1_flags
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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cpu_resume_l1_flags:
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ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
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ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
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#else
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#define cpu_v7_do_suspend 0
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#define cpu_v7_do_resume 0
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#endif
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2010-10-01 14:37:05 +00:00
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__CPUINIT
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2007-05-08 21:27:46 +00:00
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/*
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* __v7_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv7 cores.
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*
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|
|
* It is assumed that:
|
|
|
|
* - cache type register is implemented
|
|
|
|
*/
|
2010-09-17 15:42:10 +00:00
|
|
|
__v7_ca9mp_setup:
|
2008-11-06 13:23:09 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2010-09-04 09:47:48 +00:00
|
|
|
ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
|
|
|
|
ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
|
2009-11-04 12:16:38 +00:00
|
|
|
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
|
|
|
|
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
|
|
|
|
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
|
2008-11-06 13:23:09 +00:00
|
|
|
#endif
|
2010-09-17 15:42:10 +00:00
|
|
|
__v7_setup:
|
2007-05-08 21:27:46 +00:00
|
|
|
adr r12, __v7_setup_stack @ the local stack
|
|
|
|
stmia r12, {r0-r5, r7, r9, r11, lr}
|
|
|
|
bl v7_flush_dcache_all
|
|
|
|
ldmia r12, {r0-r5, r7, r9, r11, lr}
|
2009-06-01 11:50:33 +00:00
|
|
|
|
|
|
|
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
|
|
|
|
and r10, r0, #0xff000000 @ ARM?
|
|
|
|
teq r10, #0x41000000
|
2010-09-14 08:51:43 +00:00
|
|
|
bne 3f
|
2009-06-01 11:50:33 +00:00
|
|
|
and r5, r0, #0x00f00000 @ variant
|
|
|
|
and r6, r0, #0x0000000f @ revision
|
2010-09-14 08:50:03 +00:00
|
|
|
orr r6, r6, r5, lsr #20-4 @ combine variant and revision
|
|
|
|
ubfx r0, r0, #4, #12 @ primary part number
|
2009-06-01 11:50:33 +00:00
|
|
|
|
2010-09-14 08:50:03 +00:00
|
|
|
/* Cortex-A8 Errata */
|
|
|
|
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
|
|
|
|
teq r0, r10
|
|
|
|
bne 2f
|
2009-04-30 16:06:09 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_430973
|
2009-06-01 11:50:33 +00:00
|
|
|
teq r5, #0x00100000 @ only present in r1p*
|
|
|
|
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
|
|
|
orreq r10, r10, #(1 << 6) @ set IBE to 1
|
|
|
|
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
2009-04-30 16:06:15 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_458693
|
2010-09-14 08:50:03 +00:00
|
|
|
teq r6, #0x20 @ only present in r2p0
|
2009-06-01 11:50:33 +00:00
|
|
|
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
|
|
|
orreq r10, r10, #(1 << 5) @ set L1NEON to 1
|
|
|
|
orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
|
|
|
|
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
2009-04-30 16:06:20 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_460075
|
2010-09-14 08:50:03 +00:00
|
|
|
teq r6, #0x20 @ only present in r2p0
|
2009-06-01 11:50:33 +00:00
|
|
|
mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
|
|
|
|
tsteq r10, #1 << 22
|
|
|
|
orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
|
|
|
|
mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
|
2009-04-30 16:06:09 +00:00
|
|
|
#endif
|
2010-09-14 08:51:43 +00:00
|
|
|
b 3f
|
|
|
|
|
|
|
|
/* Cortex-A9 Errata */
|
|
|
|
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
|
|
|
|
teq r0, r10
|
|
|
|
bne 3f
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_742230
|
|
|
|
cmp r6, #0x22 @ only present up to r2p2
|
|
|
|
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
|
|
orrle r10, r10, #1 << 4 @ set bit #4
|
|
|
|
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
2010-09-14 08:53:02 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_742231
|
|
|
|
teq r6, #0x20 @ present in r2p0
|
|
|
|
teqne r6, #0x21 @ present in r2p1
|
|
|
|
teqne r6, #0x22 @ present in r2p2
|
|
|
|
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
|
|
orreq r10, r10, #1 << 12 @ set bit #12
|
|
|
|
orreq r10, r10, #1 << 22 @ set bit #22
|
|
|
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
2010-09-28 13:02:02 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_743622
|
|
|
|
teq r6, #0x20 @ present in r2p0
|
|
|
|
teqne r6, #0x21 @ present in r2p1
|
|
|
|
teqne r6, #0x22 @ present in r2p2
|
|
|
|
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
|
|
orreq r10, r10, #1 << 6 @ set bit #6
|
|
|
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
2011-02-18 15:36:35 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_751472
|
|
|
|
cmp r6, #0x30 @ present prior to r3p0
|
|
|
|
mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
|
|
orrlt r10, r10, #1 << 11 @ set bit #11
|
|
|
|
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
2009-06-01 11:50:33 +00:00
|
|
|
|
2010-09-14 08:51:43 +00:00
|
|
|
3: mov r10, #0
|
2007-05-08 21:27:46 +00:00
|
|
|
#ifdef HARVARD_CACHE
|
|
|
|
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
|
|
|
#endif
|
|
|
|
dsb
|
2007-07-20 10:43:02 +00:00
|
|
|
#ifdef CONFIG_MMU
|
2007-05-08 21:27:46 +00:00
|
|
|
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
|
|
|
|
mcr p15, 0, r10, c2, c0, 2 @ TTB control register
|
2010-09-04 09:47:48 +00:00
|
|
|
ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
|
|
|
|
ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
|
2011-05-26 10:22:44 +00:00
|
|
|
ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
|
|
|
|
ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
|
|
|
|
mcr p15, 0, r8, c2, c0, 1 @ load TTB1
|
2011-02-06 15:48:39 +00:00
|
|
|
ldr r5, =PRRR @ PRRR
|
|
|
|
ldr r6, =NMRR @ NMRR
|
2008-09-15 16:23:10 +00:00
|
|
|
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
|
|
|
|
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
|
2009-07-24 11:35:06 +00:00
|
|
|
#endif
|
2007-07-20 10:43:02 +00:00
|
|
|
adr r5, v7_crval
|
|
|
|
ldmia r5, {r5, r6}
|
2009-05-30 13:00:18 +00:00
|
|
|
#ifdef CONFIG_CPU_ENDIAN_BE8
|
|
|
|
orr r6, r6, #1 << 25 @ big-endian page tables
|
2010-09-16 17:00:47 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SWP_EMULATE
|
|
|
|
orr r5, r5, #(1 << 10) @ set SW bit in "clear"
|
|
|
|
bic r6, r6, #(1 << 10) @ clear it in "mmuset"
|
2009-05-30 13:00:18 +00:00
|
|
|
#endif
|
2007-07-20 10:43:02 +00:00
|
|
|
mrc p15, 0, r0, c1, c0, 0 @ read control register
|
|
|
|
bic r0, r0, r5 @ clear bits them
|
|
|
|
orr r0, r0, r6 @ set them
|
2009-07-24 11:32:56 +00:00
|
|
|
THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
|
2007-05-08 21:27:46 +00:00
|
|
|
mov pc, lr @ return to head.S:__ret
|
2008-08-28 10:22:32 +00:00
|
|
|
ENDPROC(__v7_setup)
|
2007-05-08 21:27:46 +00:00
|
|
|
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 10:52:28 +00:00
|
|
|
/* AT
|
2009-05-30 13:00:16 +00:00
|
|
|
* TFR EV X F I D LR S
|
|
|
|
* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 10:52:28 +00:00
|
|
|
* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
|
2009-05-30 13:00:16 +00:00
|
|
|
* 1 0 110 0011 1100 .111 1101 < we want
|
2007-05-08 21:27:46 +00:00
|
|
|
*/
|
2007-07-20 10:43:02 +00:00
|
|
|
.type v7_crval, #object
|
|
|
|
v7_crval:
|
2009-05-30 13:00:16 +00:00
|
|
|
crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
|
2007-05-08 21:27:46 +00:00
|
|
|
|
|
|
|
__v7_setup_stack:
|
|
|
|
.space 4 * 11 @ 11 registers
|
|
|
|
|
2010-10-01 14:37:05 +00:00
|
|
|
__INITDATA
|
|
|
|
|
2007-05-08 21:27:46 +00:00
|
|
|
.type v7_processor_functions, #object
|
|
|
|
ENTRY(v7_processor_functions)
|
|
|
|
.word v7_early_abort
|
2009-09-25 12:39:47 +00:00
|
|
|
.word v7_pabort
|
2007-05-08 21:27:46 +00:00
|
|
|
.word cpu_v7_proc_init
|
|
|
|
.word cpu_v7_proc_fin
|
|
|
|
.word cpu_v7_reset
|
|
|
|
.word cpu_v7_do_idle
|
|
|
|
.word cpu_v7_dcache_clean_area
|
|
|
|
.word cpu_v7_switch_mm
|
|
|
|
.word cpu_v7_set_pte_ext
|
2011-06-23 21:00:20 +00:00
|
|
|
.word cpu_v7_suspend_size
|
|
|
|
.word cpu_v7_do_suspend
|
|
|
|
.word cpu_v7_do_resume
|
2007-05-08 21:27:46 +00:00
|
|
|
.size v7_processor_functions, . - v7_processor_functions
|
|
|
|
|
2010-10-01 14:37:05 +00:00
|
|
|
.section ".rodata"
|
|
|
|
|
2007-05-08 21:27:46 +00:00
|
|
|
.type cpu_arch_name, #object
|
|
|
|
cpu_arch_name:
|
|
|
|
.asciz "armv7"
|
|
|
|
.size cpu_arch_name, . - cpu_arch_name
|
|
|
|
|
|
|
|
.type cpu_elf_name, #object
|
|
|
|
cpu_elf_name:
|
|
|
|
.asciz "v7"
|
|
|
|
.size cpu_elf_name, . - cpu_elf_name
|
|
|
|
.align
|
|
|
|
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
|
2010-09-17 15:42:10 +00:00
|
|
|
.type __v7_ca9mp_proc_info, #object
|
|
|
|
__v7_ca9mp_proc_info:
|
|
|
|
.long 0x410fc090 @ Required ID value
|
|
|
|
.long 0xff0ffff0 @ Mask for ID
|
2010-09-04 09:47:48 +00:00
|
|
|
ALT_SMP(.long \
|
|
|
|
PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ | \
|
|
|
|
PMD_FLAGS_SMP)
|
|
|
|
ALT_UP(.long \
|
|
|
|
PMD_TYPE_SECT | \
|
2010-09-17 15:42:10 +00:00
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ | \
|
2010-09-04 09:47:48 +00:00
|
|
|
PMD_FLAGS_UP)
|
2010-09-17 15:42:10 +00:00
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_XN | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S
Directives such as .long and .word do not magically cause the
assembler location counter to become aligned in gas. As a result,
using these directives in code sections can result in misaligned
data words when building a Thumb-2 kernel (CONFIG_THUMB2_KERNEL).
This is a Bad Thing, since the ABI permits the compiler to assume
that fundamental types of word size or above are word- aligned when
accessing them from C. If the data is not really word-aligned,
this can cause impaired performance and stray alignment faults in
some circumstances.
In general, the following rules should be applied when using data
word declaration directives inside code sections:
* .quad and .double:
.align 3
* .long, .word, .single, .float:
.align (or .align 2)
* .short:
No explicit alignment required, since Thumb-2
instructions are always 2 or 4 bytes in size.
immediately after an instruction.
In this specific case, we can achieve the desired alignment by
forcing a 32-bit branch instruction using the W() macro, since the
assembler location counter is already 32-bit aligned in this case.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-29 18:43:25 +00:00
|
|
|
W(b) __v7_ca9mp_setup
|
2010-09-17 15:42:10 +00:00
|
|
|
.long cpu_arch_name
|
|
|
|
.long cpu_elf_name
|
2010-10-07 18:34:04 +00:00
|
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
|
2010-09-17 15:42:10 +00:00
|
|
|
.long cpu_v7_name
|
|
|
|
.long v7_processor_functions
|
|
|
|
.long v7wbi_tlb_fns
|
|
|
|
.long v6_user_fns
|
|
|
|
.long v7_cache_fns
|
|
|
|
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
|
|
|
|
|
2007-05-08 21:27:46 +00:00
|
|
|
/*
|
|
|
|
* Match any ARMv7 processor core.
|
|
|
|
*/
|
|
|
|
.type __v7_proc_info, #object
|
|
|
|
__v7_proc_info:
|
|
|
|
.long 0x000f0000 @ Required ID value
|
|
|
|
.long 0x000f0000 @ Mask for ID
|
2010-09-04 09:47:48 +00:00
|
|
|
ALT_SMP(.long \
|
|
|
|
PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ | \
|
|
|
|
PMD_FLAGS_SMP)
|
|
|
|
ALT_UP(.long \
|
|
|
|
PMD_TYPE_SECT | \
|
2007-05-08 21:27:46 +00:00
|
|
|
PMD_SECT_AP_WRITE | \
|
2009-11-01 17:44:24 +00:00
|
|
|
PMD_SECT_AP_READ | \
|
2010-09-04 09:47:48 +00:00
|
|
|
PMD_FLAGS_UP)
|
2007-05-08 21:27:46 +00:00
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_XN | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S
Directives such as .long and .word do not magically cause the
assembler location counter to become aligned in gas. As a result,
using these directives in code sections can result in misaligned
data words when building a Thumb-2 kernel (CONFIG_THUMB2_KERNEL).
This is a Bad Thing, since the ABI permits the compiler to assume
that fundamental types of word size or above are word- aligned when
accessing them from C. If the data is not really word-aligned,
this can cause impaired performance and stray alignment faults in
some circumstances.
In general, the following rules should be applied when using data
word declaration directives inside code sections:
* .quad and .double:
.align 3
* .long, .word, .single, .float:
.align (or .align 2)
* .short:
No explicit alignment required, since Thumb-2
instructions are always 2 or 4 bytes in size.
immediately after an instruction.
In this specific case, we can achieve the desired alignment by
forcing a 32-bit branch instruction using the W() macro, since the
assembler location counter is already 32-bit aligned in this case.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-29 18:43:25 +00:00
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W(b) __v7_setup
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2007-05-08 21:27:46 +00:00
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.long cpu_arch_name
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.long cpu_elf_name
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2010-07-05 13:53:10 +00:00
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
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2007-05-08 21:27:46 +00:00
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.long cpu_v7_name
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.long v7_processor_functions
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2007-05-18 10:25:31 +00:00
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.long v7wbi_tlb_fns
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2007-05-08 21:27:46 +00:00
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.long v6_user_fns
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.long v7_cache_fns
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.size __v7_proc_info, . - __v7_proc_info
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